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Volumn 22, Issue 1, 2001, Pages 32-34

Back gate effects on threshold voltage sensitivity to SOI thickness in fully-depleted SOI MOSFETs

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; GATES (TRANSISTOR); SENSITIVITY ANALYSIS; SILICON ON INSULATOR TECHNOLOGY; THICK FILM DEVICES; THICKNESS MEASUREMENT; THRESHOLD VOLTAGE;

EID: 0035120828     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.892435     Document Type: Article
Times cited : (15)

References (11)
  • 2
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    • Limitations on threshold adjustment by backgating in fully depleted silicon-on-insulator metal-oxide semiconductor field effect transistors
    • N. G. Tarr et al, "Limitations on threshold adjustment by backgating in fully depleted silicon-on-insulator metal-oxide semiconductor field effect transistors," J. Vac. Sci. Technol. A, vol. 16, pp. 838-842, 1998.
    • (1998) J. Vac. Sci. Technol. A , vol.16 , pp. 838-842
    • Tarr, N.G.1
  • 3
    • 0029482142 scopus 로고    scopus 로고
    • High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: Ψ) SOI wafer
    • M. Horiuchi, T. Teshima, K. Tokumasu, and K. Yamaguchi, "High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: Ψ) SOI wafer," in 1995 VLSI Technol. Symp., pp. 33-34.
    • 1995 VLSI Technol. Symp. , pp. 33-34
    • Horiuchi, M.1    Teshima, T.2    Tokumasu, K.3    Yamaguchi, K.4
  • 4
    • 84886447996 scopus 로고    scopus 로고
    • Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
    • H.-S. P. Wong, K.K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," in IEDM Tech. Dig., 1997, pp. 427-430.
    • (1997) IEDM Tech. Dig. , pp. 427-430
    • Wong, H.-S.P.1    Chan, K.K.2    Taur, Y.3
  • 5
    • 0032284102 scopus 로고    scopus 로고
    • Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
    • H.-S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation." in IEDM Tech. Dig., 1998, pp. 407-410.
    • (1998) IEDM Tech. Dig. , pp. 407-410
    • Wong, H.-S.P.1    Frank, D.J.2    Solomon, P.M.3
  • 6
    • 0033280988 scopus 로고    scopus 로고
    • SON (silicon on nothing)-A new device archiecture for the ULSI era
    • M. Jurczak et al., "SON (silicon on nothing)-A new device archiecture for the ULSI era," in 1999 VLSI Technol. Symp., 1999, pp. 29-30.
    • (1999) 1999 VLSI Technol. Symp. , pp. 29-30
    • Jurczak, M.1
  • 8
    • 0026939774 scopus 로고
    • Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers
    • J. Chen et al., "Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers," IEEE Trans. Electron Devices, vol. 39, pp. 2346-2353, 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 2346-2353
    • Chen, J.1
  • 9
    • 84954137737 scopus 로고
    • Quantum-mechanical threshold voltage shifts of MOSFET's caused by high levels of channel doping
    • M. J. van Dort et al., "Quantum-mechanical threshold voltage shifts of MOSFET's caused by high levels of channel doping," in IEDM Tech. Dig., 1991, pp. 495-499.
    • (1991) IEDM Tech. Dig. , pp. 495-499
    • Van Dort, M.J.1
  • 10
    • 0020830319 scopus 로고
    • Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's
    • H.-K. Lim and J. G. Possum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's," IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , pp. 1244-1251
    • Lim, H.-K.1    Possum, J.G.2
  • 11
    • 0028257321 scopus 로고
    • Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance
    • Jan.
    • M. Chan et al., "Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance," IEEE Electron Device Lett., vol. 15, pp. 22-24, Jan. 1994.
    • (1994) IEEE Electron Device Lett. , vol.15 , pp. 22-24
    • Chan, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.