POSET timing and its application to the synthesis and verification of gate-level timed circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 6, 1999, Pages 769-786

  Myers, Chris J ^a,d   Rokicki, Tomas G ^b   Meng, Teresa H Y ^c  

^a IEEE   (United States)

^b Department of Electrical and Computer Engineering   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

^d STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL GEOMETRY; COMPUTER AIDED DESIGN; ELECTRIC NETWORK SYNTHESIS;

GATE-LEVEL TIMED CIRCUITS; TIMED ASYNCHRONUOS CIRCUITS;

TIMING CIRCUITS;

EID: 0032652863     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.766727     Document Type: Article

References (40)

1. A. J. Martin, "Programming in VLSI: From communicating processes to delay-insensitive VLSI circuits," in UT Year of Programming Institute on Concurrent Programming, C. A. R. Hoare, Ed. Reading, MA: Addison-Wesley, 1990.
2. T.-A. Chu, Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications, Ph.D. dissertation, Massachusetts Inst. Technol., Cambridge, 1987.
3. T. H.-Y. Meng, R. W. Brodersen, and D. G. Messershmitt, "Automatic synthesis of asynchronous circuits from high-level specifications," IEEE Trans. Computer-Aided Design, vol. 8, pp. 1185-1205, Nov. 1989.
4. G. Borriello, "A new specification methodology and its applications to transducer synthesis," Ph.D. dissertation, Univ. California, Berkeley, 1988.
5. P. Vanbekbergen, "Synthesis of asynchronous controllers from graphtheoretic specifications," Ph.D. dissertation, Katholieke Unviversiteit Leuven, Belgium, Sept. 1993.
6. L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli, "Algorithms for synthesis of hazard-free asynchronous circuits," presented at 28th ACM/IEEE Design Automation Conf., 1991.
7. C. J. Myers and T. H.-Y. Meng, "Synthesis of timed asynchronous circuits," IEEE Trans. VLSI Syst., vol. 1, pp. 106-119, June 1993.
8. J. R. Burch, "Trace algebra for automatic verification of real-time concurrent systems," Ph.D. dissertation, Carnegie Mellon University, Pittsburgh, PA, 1992.
9. P. Merlin and D. J. Faber, "Recoverability of communication protocols," IEEE Trans. Commun., vol. 24, no. 9, 1976.
10. T. G. Rokicki, "Representing and modeling circuits," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1993.
11. R. Alur, "Techniques for automatic verification of real-time systems," Ph.D. dissertation, Stanford Univ, Stanford, CA, Aug. 1991.
12. T. A. Henzinger, "The temporal specification and verification of real-time systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1991.
13. T. A. Henzinger, Z. Manna, and A. Pnueli, "What good are digital clocks?," in ICALP 92: Automata, Languages, and Programming. Berlin, Germany: Springer-Verlag, 1992, pp. 545-547.
14. H. Hulgaard and S. M. Burns, "Bounded delay timing analysis of a class of CSP programs with choice," in Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems. Nov. 1994, pp. 2-11.
15. E. A. Walkup and G. Borriello, "Interface timing verification with combined max and linear constraints," presented at Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Sept. 1993.
16. J. Gunawardena, "Timing analysis of digital circuits of min-max functions," presented at Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Sept. 1993.
17. D. L. Dill, "Timing assumptions and verification of finite-state concurrent systems," presented at Workshop on Automatic Verification Methods for Finite-State Systems, 1989.
18. H. R. Lewis, "Finite-state analysis of asynchronous circuits with bounded temporal uncertainty," Harvard Univ., Cambridge, MA, Tech. Rep., July 1989.
19. B. Berthomieu and M. Diaz, "Modeling and verification of timedependent systems using time petri nets," IEEE Trans. Software Eng., vol. 17, Mar. 1991.
20. R. Alur, C. Courcoubetis, D. Dill, N. Halbwachs, and H. Wong-Toi, "An implementation of three algorithms for timing verification based on automata emptiness," in Proc. Real-Time Systems Symp., 1992, pp. 157-166.
21. T. Henzinger, X. Nicollin, J. Sifakis, and S. Yovine, "Symbolic modelchecking for real-time systems," presented at 7th Symp. Logics in Computers Science, 1992.
22. N. Halbwachs, "Delay analysis in synchronous programs," in Computer Aided Verification, Costas Courcoubetis, Ed. Berlin, Germany: Springer-Verlag, 1993, pp. 333-346.
23. A. Valmari, "A stubborn attack on state explosion," in Proc. Int. Conf. Computer-Aided Verification, June 1990, pp. 176-185.
24. P. Godefroid, "Using partial orders to improve automatic verification methods," in Proc. Int. Conf. Computer-Aided Verification, June 1990, pp. 176-185.
25. K. McMillan, "Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits," in Proc. International Workshop on Computer Aided Verification, in Lecture Notes in Computer Science, vol. 663, G. V. Bochman and D. K. Probst, Eds. Berlin, Germany: Springer-Verlag, 1992, pp. 164-177.
26. T. Yoneda, A. Shibayama, B. Schlingloff, and E. M. Clarke, "Efficient verification of parallel real-time systems," in Computer Aided Verification, Costas Courcoubetis, Ed. Berlin, Germany: Springer-Verlag, 1993, pp. 321-332.
27. C. J. Myers, "Computer-aided synthesis and verification of gate-level timed circuits," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1995.
28. P. A. Beerel, C. J. Myers, and T. H.-Y. Meng, "Covering conditions and algorithms for the synthesis of speed-independent circuits," IEEE Trans. Computer-Aided Design, vol. 17, Mar. 1998.
29. P. Beerel and T. H.-Y. Meng, "Automatic gate-level synthesis of speed-independent circuits," in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 1992, pp. 581-587.
30. A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," in Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 56-62.
31. K.-J. Lin, J.-W. Kuo, and C.-S. Lin, "Direct synthesis of hazard-free asynchronous circuits from STG's based on lock relation and MGdecomposition approach," in Proc. Eur. Design and Test Conf., 1994, pp. 178-183.
32. K. Y. Yun, "Synthesis of asynchronous controllers for heterogeneous systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1994.
33. C. J. Myers and A. J. Martin, "The design of an asynchronous memory management," California Institute of Technology, Pasadena, CA, Tech. Rep. CS-TR-93-30, 1993.
34. S. M. Nowick, K. Y. Yun, and D. L. Dill, "Practical asynchronous controller design," presented at Int. Conf. Computer Design, ICCD-1992, 1992.
35. K. Y. Yun, private communication, 1993.
36. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. SangiovanniVincentelli, "SIS: A system for sequential circuit synthesis," Univ. California, Berkeley, Tech. Rep. UCB/ERL M92/41, May 1992.
37. D. L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. Cambridge, MA: MIT Press, 1989.
38. C. L. Seitz, "System timing," in Introduction to VLSI Systems, Carver A. Mead and Lynn A. Conway, Eds. Reading, MA: Addison-Wesley, ch. 7, 1980.
39. T. G. Rokicki and C. J. Myers, "Automatic verification of timed circuits," in Proc. Int. Conf. Computer-Aided Verification, 1994, pp. 468-480.
40. C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, "Automatic synthesis of gate-level timed circuits with choice," in Proc. 16th Conf. Advanced Research in VLSI, 1995, pp. 42-58.