Verification of asynchronous circuits using time Petri net unfolding

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 59-62

  Semenov, Alexei ^a   Yakovlev, Alexandre ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; LOGIC GATES; MATHEMATICAL MODELS; PETRI NETS;

ASYNCHRONOUS CIRCUITS; TIME PETRI NET UNFOLDING;

LOGIC CIRCUITS;

EID: 0029708231     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240530     Document Type: Conference Paper

References (12)