Dynamic timing analysis considering power supply noise effects

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 137-143

  Jiang, Yi Min ^a   Krstić, Angela ^b   Cheng, Kwang Ting ^b  

^a SYNOPSYS INC   (United States)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS;

CIRCUIT DELAYS; CIRCUIT PERFORMANCE; DEEP SUB-MICRON DESIGNS; DYNAMIC TIMING ANALYSIS; INPUT PATTERNS; POWER-SUPPLY NOISE; PROPAGATION DELAYS; TIMING ANALYSIS;

TIMING CIRCUITS;

EID: 84950154686     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838866     Document Type: Conference Paper

References (11)

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