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Volumn 2001-January, Issue , 2001, Pages 257-258

RC power bus maximum voltage drop in digital VLSI circuits

Author keywords

[No Author keywords available]

Indexed keywords

SENSITIVITY ANALYSIS; TIMING CIRCUITS;

EID: 77951189067     PISSN: 19483287     EISSN: 19483295     Source Type: Journal    
DOI: 10.1109/ISQED.2001.915238     Document Type: Article
Times cited : (5)

References (3)
  • 1
    • 0034478054 scopus 로고    scopus 로고
    • Simulation and optimization of the power distribution network in VLSI circuits
    • Nov
    • G. Bai, S. Bobba and I.N. Hajj "Simulation and Optimization of the Power Distribution Network in VLSI Circuits," Proc. of ICCAD, Nov. 2000
    • (2000) Proc. of ICCAD
    • Bai, G.1    Bobba, S.2    Hajj, I.N.3
  • 2
    • 0002885199 scopus 로고    scopus 로고
    • Power bus maximum voltage drop estimation in digital VLSI circuit
    • March
    • G. Bai, S. Bobba and I.N. Hajj "Power Bus Maximum Voltage Drop Estimation in digital VLSI Circuit," Proc. of ISQED, pp. 263-268, March 2000.
    • (2000) Proc. of ISQED , pp. 263-268
    • Bai, G.1    Bobba, S.2    Hajj, I.N.3
  • 3
    • 0029358733 scopus 로고
    • Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
    • August
    • H. Kriplani, F.N. Najm and I.N. Hajj "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution," in IEEE Trans. on CAD, Vol. 14, No. 8, pp. 998-1012, August 1995.
    • (1995) IEEE Trans. on CAD , vol.14 , Issue.8 , pp. 998-1012
    • Kriplani, H.1    Najm, F.N.2    Hajj, I.N.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.