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Volumn 2001-January, Issue , 2001, Pages 257-258
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RC power bus maximum voltage drop in digital VLSI circuits
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Author keywords
[No Author keywords available]
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Indexed keywords
SENSITIVITY ANALYSIS;
TIMING CIRCUITS;
CIRCUIT TIMING;
GATE CURRENT;
OPTIMIZATION PROCEDURES;
POWER BUS;
SUB-INTERVAL;
VOLTAGE DROP;
VLSI CIRCUITS;
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EID: 77951189067
PISSN: 19483287
EISSN: 19483295
Source Type: Journal
DOI: 10.1109/ISQED.2001.915238 Document Type: Article |
Times cited : (5)
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References (3)
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