Design and implementation of a parity-based BIST scheme for FPGA global interconnects

Canadian Conference on Electrical and Computer Engineering

Volumn 2, Issue , 2001, Pages 1251-1258

  Sun, Xiaoling ^a   Xu, Susan ^a   Xu, Jian ^a   Trouborst, Pieter ^b  

^a UNIVERSITY OF ALBERTA   (Canada)

^b NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DESIGN; MAPPING; ROUTERS;

GLOBAL INTERCONNECTS;

INTERCONNECTION NETWORKS;

EID: 0034838642     PISSN: 08407789     EISSN: None     Source Type: Journal    
DOI: 10.1109/CCECE.2001.933621     Document Type: Article

References (13)

1. Novel technique for built-in self-test of FPGA interconnects
2. Diagnosis of interconnects and FPICs using a structured walking-1 approach
3. Diagnosing programmable interconnect systems for FPGAs
4. On the diagnosis of programmable interconnect systems: Theory and application
5. A test methodology for interconnect structures of LUT-based FPGAs
6. Testing the interconnect of RAM-based FPGAs
7. Built-in self-test of FPGA interconnect
8. A diagnosis method for interconnects in SRAM based FPGAs
9. Testing the local interconnect resources of SRAM-based FPGAs
10. Implementation of a BIST scheme to testing FPGA global interconnections