Diagnosis method for interconnects in SRAM based FPGAs

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 278-282

  Yu, Yinlei ^a   Xu, Jian ^a   Huang, Wei Kang ^a   Lombardi, Fabrizio ^a  

^a FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

STATIC RANDOM ACCESS MEMORY (SRAM);

ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE MODELS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032296208     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. M. Renovell, J. Figueras and Y. Zorian. "Testing the Interconnect Structure of Unconfigurated FPGA", IEEE European Test Workshop, pp. 125129, Sete, FRANCE, June 1996.
2. W. K. Huang, X. T. Chen and F. Lombardi, "On the Diagnosis of Programmable Interconnect Systems: Theory and Application" Proc. 14th IEEE VLSI Test Symposium, pp.204-209, Princeton, NJ, USA, May 1996.
3. M. Renovell, et. al, "Testing the interconnect of RAM-Based FPGAs" IEEE D&T of Computers, pp. 45-50, January-March, 1998
4. H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue and H. Fujiwara, "A test methodology for interconnect structures of LUT-based FPGAs". Proc. of Asia Test Symposium, 1996.
5. H. Michinishi, et. al., "Testing for the programming circuits of LUT based FPGAs", pp.242-247, Proc. of Asia Test Symposium, Japan, November, 1997.
6. W. H. Kautz, "Testing for Fault in Wiring Networks", IEEE Trans, on Computers, Vol.C-23, No.4, pp.358-363, 1974.