Efficient representation of interconnection length distributions using generating polynomials

International Workshop on System-Level Interconnect Prediction (SLIP 2000)

Volumn , Issue , 2000, Pages 99-105

  Stroobandt, Dirk ^a,c   Van Marck, Herwig ^b  

^a GHENT UNIVERSITY   (Belgium)

^b Ctr for Evolvable Lang Engineering   (Belgium)

^c FUND FOR SCIENTIFIC RESEARCH   (Belgium)

Author keywords

Enumeration; Generating polynomials; Interconnect length distributions; VLSI CAD

Indexed keywords

COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS; POLYNOMIALS; PROBABILITY; PROBLEM SOLVING;

INTERCONNECTION LENGTH DISTRIBUTIONS;

VLSI CIRCUITS;

EID: 0034592477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/333032.333039     Document Type: Conference Paper

References (22)

1. H. B. Bakoglu. Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990.
2. A. Caldwell, A. B. Kahng, F. Koushanfar, H. Lu, I. Markov, M. Oliver, and D. Stroobandt. GTX: The MARCO GSRC technology extrapolation system. To be published in Proc. ACM/IEEE Design Automation Conf. http://vlsicad.cs.ucla.edu/GSRC/GTX/, 2000.
3. P. Christie and D. Stroobandt. The interpretation and application of Rent's rule. IEEE Trans. on VLSI Systems, Special Lssue on System-Level Interconnect Prediction, September 2000.
4. J. A. Davis, V. K. De, and J. D. Meindl. A stochastic wire-length distribution for gigascale integration (GSI) - PART I: Derivation and validation. IEEE Trans. on Electron Devices, 45 (3): pages 580-589, March 1998.
5. W. E. Donath. Placement and average interconnection lengths of computer logic. IEEE Trans. Circuits & Syst., vol. CAS-26: pages 272-277, 1979.
6. J. C. Eble, V. K. De, D. S. Wills, and J. D. Meindl. A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001. In Proc. 9th Annual IEEE Intl. ASIC Conf., pages 193-196, 1996.
7. B. M. Geuskens. Modeling the influence of multilevel interconnect on chip performance, 1997. Ph.D. thesis, Rensselaer Polytechnic Institute, Troy, New York, http://latte.cie.rpi.edu/ripe.html.
8. I. S. Gradshteyn and I. M. Ryzhik. Table of Integrals, Series, and Products. Academic Press, 1980. Corrected and enlarged edition.
9. R. P. Grimaldi. Discrete and Combinatorial Mathematics. Addison-Wesley Publishing Co., 1986.
10. B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic graphs. IEEE Trans. on Comput., vol. C-20: pages 1469-1479, 1971.
11. H. M. Ozaktas and J. Goodman. Implications of inteconnection theory for optical digital computing. Applied Optics, vol. 31: pages 5559-5567, 1992.
12. D. Stroobandt. Analytical methods for a priori wire length estimates in computer systems, 1998. Ph.D. thesis (translated from Dutch), Ghent University.
13. D. Stroobandt. Tutorial: A priori wire length estimates based on Rent's rule. In Workshop on System-Level Interconnect Prediction, pages 3-50, 1999.
14. D. Stroobandt and J. Van Campenhout. Estimatig interconnection lengths in three-dimensional computer systems. IEICE Trans. on Inf. & Syst., Special Issue on Synthesis and Verification of Hardware Design, vol. E80-D (no. 10): pages 1024-1031, October 1997.
15. D. Stroobandt and J. Van Campenhout. Accurate interconnection length estimations for predictions early in the design cycle. VLSI Design, Special Issue on Physical Design in Deep Submicron, vol. 10, 1999.
16. D. Stroobandt, H. Van Marck, and J. Van Campenhout. On the use of generating polynomials for the representation of interconnection length distributions. In Proc. 4th, Intl. Workshop on Symbolic Methods and Applications in Circuit Design (SMACD '96), pages 70-73. Katholieke Universiteit Leuven, October 1996.
17. D. Stroobandt, H. Van Marck, and J. Van Campenhout. Estimating logic cell to I/O pad lengths in computer systems. In Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pages 192-198. S. Insatsu, Osaka, Japan, December 1997.
18. D. Sylvester and K. Keutzer. System-level performance modeling with BACPAC - Berkeley advanced chip performance calculator. In Workshop on System-Level Interconnect Prediction, pages 109-114, 1999.
19. J. Van Campenhout, H. Van Marck, J. Depreitere, and J. Dambre. Optoelectronic FPGAs. IEEE Journal of Selected Topics in Quantum Electronics on Smart Photonic Components, Interconnects, and Processing, vol. 5 (no. 2): pages 306-315, March/April 1999.
20. H. Van Marck. Kwantitatieve studie en modellering van opto-elektronische driedimensionale interconnectiestructuren, 2000. Ph.D. dissertation (in Dutch), Ghent University, Belgium.
21. H. Van Marck and J. Van Campenhout. Modeling and evaluating optoelectronic architectures. In Optoelectronics II, volume 2153 of SPIE Proc. Series, pages 307-314, SPIE, 1994.
22. R. Vich. Z Transform Theory and Applications. D. Reidel Publishing Company, 1987.