-
2
-
-
0023346895
-
A study of channel avalanche breaksown in scaled n-MOSFETs
-
Laux S.E., Gaensslen F.H. A study of channel avalanche breaksown in scaled n-MOSFETs. IEEE Trans Electron Dev. ED-34(5):1987;1066-1073.
-
(1987)
IEEE Trans Electron Dev
, vol.34
, Issue.5
, pp. 1066-1073
-
-
Laux, S.E.1
Gaensslen, F.H.2
-
3
-
-
0030128946
-
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
-
Ker M.-D., Wu C.-Y., Chang H.-H. Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI. IEEE Trans Electron Dev. 43(4):1996;588-598.
-
(1996)
IEEE Trans Electron Dev
, vol.43
, Issue.4
, pp. 588-598
-
-
Ker, M.-D.1
Wu, C.-Y.2
Chang, H.-H.3
-
4
-
-
0034159376
-
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
-
Ker M.-D., Chang H.-H. Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger. Solid-State Electron. 44:2000;425-445.
-
(2000)
Solid-State Electron
, vol.44
, pp. 425-445
-
-
Ker, M.-D.1
Chang, H.-H.2
-
5
-
-
0033741133
-
Novel diode-chain triggering SCR circuits for ESD protection
-
Jang S.-L., Gau M.-S., Lin C.-K. Novel diode-chain triggering SCR circuits for ESD protection. Solid-State Electron. 44:2000;1297-1303.
-
(2000)
Solid-State Electron
, vol.44
, pp. 1297-1303
-
-
Jang, S.-L.1
Gau, M.-S.2
Lin, C.-K.3
-
6
-
-
0029482707
-
An ESD protection scheme for deep submicron ULSI circuits
-
Sharma U, Campbell J, Choe H, Kuo C, Prinz E, Raghunathan E, Gardner P, Avery L. An ESD protection scheme for deep submicron ULSI circuits. Symp VLSI Tech Dig, 1995. p. 85-6.
-
(1995)
Symp VLSI Tech Dig
, pp. 85-86
-
-
Sharma, U.1
Campbell, J.2
Choe, H.3
Kuo, C.4
Prinz, E.5
Raghunathan, E.6
Gardner, P.7
Avery, L.8
-
8
-
-
0031249221
-
Using an SCR as ESD protection without latch-up danger
-
Notermans G., Kuper F., Luchies J.-M. Using an SCR as ESD protection without latch-up danger. Microelectron Reliab. 37(10/11):1997;1457-1460.
-
(1997)
Microelectron Reliab
, vol.37
, Issue.10-11
, pp. 1457-1460
-
-
Notermans, G.1
Kuper, F.2
Luchies, J.-M.3
-
9
-
-
0023435530
-
Latchup performance of retrograde and conventional n-well CMOS technologies
-
Lewis A.G., Martin R.A., Huang T.-Y., Chen J.Y., Koyanagi M. Latchup performance of retrograde and conventional n-well CMOS technologies. IEEE Trans Electron Dev. ED-34(10):1987;2156-2163.
-
(1987)
IEEE Trans Electron Dev
, vol.34
, Issue.10
, pp. 2156-2163
-
-
Lewis, A.G.1
Martin, R.A.2
Huang, T.-Y.3
Chen, J.Y.4
Koyanagi, M.5
-
10
-
-
0024055906
-
Optimization of silicon bipolar transistors for high current gain at low temperatures
-
Woo J.C.S., Plummer J.D. Optimization of silicon bipolar transistors for high current gain at low temperatures. IEEE Trans Electron Dev. 35(8):1988;1311-1321.
-
(1988)
IEEE Trans Electron Dev
, vol.35
, Issue.8
, pp. 1311-1321
-
-
Woo, J.C.S.1
Plummer, J.D.2
-
11
-
-
0025508497
-
Frequency response of advanced silicon bipolar transistors at low temperature
-
Jenkins KA. Frequency response of advanced silicon bipolar transistors at low temperature. Solid-State Electron 1990;37:2243-49.
-
(1990)
Solid-State Electron
, vol.37
, pp. 2243-2249
-
-
Jenkins, K.A.1
-
12
-
-
0022581286
-
Temperature dependence of latch-up phenomena in scaled CMOS structures
-
Sangiorgi E., Johnston R.L., Pinto M.R., Bechtold P.E., Fichtner W. Temperature dependence of latch-up phenomena in scaled CMOS structures. IEEE Electron Dev Lett. EDL-7:1986;28.
-
(1986)
IEEE Electron Dev Lett
, vol.7
, pp. 28
-
-
Sangiorgi, E.1
Johnston, R.L.2
Pinto, M.R.3
Bechtold, P.E.4
Fichtner, W.5
-
13
-
-
0021377786
-
Temperature dependence of latch-up in CMOS circuits
-
Dooley J.G., Jaeger R.C. Temperature dependence of latch-up in CMOS circuits. IEEE Electron Dev Lett. EDL-5:1984;41.
-
(1984)
IEEE Electron Dev Lett
, vol.5
, pp. 41
-
-
Dooley, J.G.1
Jaeger, R.C.2
-
15
-
-
0023331957
-
An analytical model of holding voltage for latchup in epitaxial CMOS
-
Seitchik J., Chatterjee A., Yang P. An analytical model of holding voltage for latchup in epitaxial CMOS. IEEE Electron Dev Lett. EDL-8:1987;157.
-
(1987)
IEEE Electron Dev Lett
, vol.8
, pp. 157
-
-
Seitchik, J.1
Chatterjee, A.2
Yang, P.3
-
16
-
-
85031523348
-
-
MS Thesis, National Taiwan University of Science and Technology, Taiwan
-
Gau M-S. MS Thesis, National Taiwan University of Science and Technology, Taiwan, 1999.
-
(1999)
-
-
Gau, M.-S.1
-
17
-
-
0000344253
-
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35 um silicide CMOS process
-
Ker M.-D., Lo W.-Y. Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35 um silicide CMOS process. IEEE Trans Solid-State Circ. 35(4):2000;601-611.
-
(2000)
IEEE Trans Solid-State Circ
, vol.35
, Issue.4
, pp. 601-611
-
-
Ker, M.-D.1
Lo, W.-Y.2
-
18
-
-
0031176814
-
A novel on-chip electrostatic (ESD) protection with common discharge line for high-speed CMOS LSI's
-
Narita K., Horiguchi Y., Nakamura K. A novel on-chip electrostatic (ESD) protection with common discharge line for high-speed CMOS LSI's. IEEE Trans Electron Dev. 44(7):1997;1124-1129.
-
(1997)
IEEE Trans Electron Dev
, vol.44
, Issue.7
, pp. 1124-1129
-
-
Narita, K.1
Horiguchi, Y.2
Nakamura, K.3
-
19
-
-
0030836964
-
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs
-
Ker M.-D., Chang H.-H., Wu C.-Y. A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs. IEEE Trans Solid-State Circ. 32(1):1997;38-50.
-
(1997)
IEEE Trans Solid-State Circ
, vol.32
, Issue.1
, pp. 38-50
-
-
Ker, M.-D.1
Chang, H.-H.2
Wu, C.-Y.3
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