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Volumn 44, Issue 7, 2000, Pages 1297-1303

Novel diode-chain triggering SCR circuits for ESD protection

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTING SILICON; SEMICONDUCTOR DIODES;

EID: 0033741133     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(00)00016-2     Document Type: Article
Times cited : (30)

References (11)
  • 3
    • 0033100138 scopus 로고    scopus 로고
    • CMOS technology-year 2010 and beyond
    • Iwai H. CMOS technology-year 2010 and beyond. IEEE J Solid State Circuits. 34:1999;357-366.
    • (1999) IEEE J Solid State Circuits , vol.34 , pp. 357-366
    • Iwai, H.1
  • 4
    • 0032306570 scopus 로고    scopus 로고
    • Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes
    • Chen J.Z., Amerasekera E.A., Duvvury C. Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes. IEEE Trans Electron Dev. 45(12):1998;2448-2456.
    • (1998) IEEE Trans Electron Dev , vol.45 , Issue.12 , pp. 2448-2456
    • Chen, J.Z.1    Amerasekera, E.A.2    Duvvury, C.3
  • 5
    • 0032309711 scopus 로고    scopus 로고
    • How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on
    • EOS-20
    • Ker M-D, Chang H-H. How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on. EOS/ESD Symp Proc, EOS-20, 1998.
    • (1998) EOS/ESD Symp Proc
    • Ker, M.-D.1    Chang, H.-H.2
  • 6
    • 0030128946 scopus 로고    scopus 로고
    • Complementary-LVTSCR ESD protect circuit for submicron CMOS VLSI/ULSI
    • Ker M.-.D., Wu C.-.Y., Chang H.-.H. Complementary-LVTSCR ESD protect circuit for submicron CMOS VLSI/ULSI. IEEE Trans Electron Dev. 43(4):1996;588-598.
    • (1996) IEEE Trans Electron Dev , vol.43 , Issue.4 , pp. 588-598
    • Ker, M.-d.1    Wu, C.-y.2    Chang, H.-h.3
  • 7
    • 0025953251 scopus 로고
    • A low-voltage triggering SCR for on-chip ESD protection at output and input pads
    • Chatterjee A., Polgreen T. A low-voltage triggering SCR for on-chip ESD protection at output and input pads. IEEE Electron Dev Letts. 12(1):1991;21-22.
    • (1991) IEEE Electron Dev Letts , vol.12 , Issue.1 , pp. 21-22
    • Chatterjee, A.1    Polgreen, T.2
  • 8
    • 0030836964 scopus 로고    scopus 로고
    • A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
    • Ker M.-D., Chang H.-H., Wu C.-Y. A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's. IEEE J Solid State Circuits. 32(l):1997;38-51.
    • (1997) IEEE J Solid State Circuits , vol.32 , Issue.L , pp. 38-51
    • Ker, M.-D.1    Chang, H.-H.2    Wu, C.-Y.3
  • 9
    • 0029705786 scopus 로고    scopus 로고
    • Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits
    • Chen JZ, Zhang XY, Amerasekera EA, Vrotsos T. Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits. Proc IRPS, 1996, p. 227.
    • (1996) Proc IRPS , pp. 227
    • Chen, J.Z.1    Zhang, X.Y.2    Amerasekera, E.A.3    Vrotsos, T.4
  • 10
    • 0029342053 scopus 로고
    • Complementary-SCR ESD protection circuit with inter-digitated finger-type layout for input pads of submicron CMOS IC's
    • Ker M.-.D., Wu C.-.Y. Complementary-SCR ESD protection circuit with inter-digitated finger-type layout for input pads of submicron CMOS IC's. IEEE Trans Electron Dev. 42(7):1995;1297-1304.
    • (1995) IEEE Trans Electron Dev , vol.42 , Issue.7 , pp. 1297-1304
    • Ker, M.-d.1    Wu, C.-y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.