Timing-constrained incremental routing algorithm for symmetrical FPGAs

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 170-174

  Raman, Srilata ^a   Liu, C L ^a   Jones, L G ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; COMPUTATIONAL METHODS; CONSTRAINT THEORY; LOGIC DESIGN; MATHEMATICAL MODELS; RESOURCE ALLOCATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); TIMING CONSTRAINED INCREMENTAL ROUTING ALGORITHM;

LOGIC GATES;

EID: 0029777828     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)