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Volumn 147, Issue 6, 2000, Pages 391-396

Partitioning methodology for dynamically reconfigurable embedded systems

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER HARDWARE; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION;

EID: 0034313232     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:20000871     Document Type: Article
Times cited : (33)

References (26)
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  • 2
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    • BROWN, S., and ROSE, J.: FPGA and CPLD architectures: A tutorial, IEEE Design Test Comput., 1996, 13, (2), pp. 42-57
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    • When DSPs and FPGAs meet: Optimising image processing architectures
    • COLET, P.: When DSPs and FPGAs meet: Optimising image processing architectures, Adv. Imaging, 1997, 12, (9), pp. 14-18
    • (1997) Adv. Imaging , vol.12 , Issue.9 , pp. 14-18
    • Colet, P.1
  • 6
    • 0028768023 scopus 로고
    • A high-performance microarchitecture with hardware-programmable functional units
    • RAZADAN, R., and SMITH, M.D.: A high-performance microarchitecture with hardware-programmable functional units. Proceedings of MICRO-27, 1994, pp. 172-180
    • (1994) Proceedings of MICRO-27 , pp. 172-180
    • Razadan, R.1    Smith, M.D.2
  • 7
    • 0027561268 scopus 로고
    • Processor reconfiguration through instruction-set metamorphosis
    • ATHANAS, P.M., and SILVERMAN, H.F.: Processor reconfiguration through instruction-set metamorphosis, IEEE Computer, 1993, 26, (3), pp. 11-18
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    • Software acceleration using programmable hardware devices
    • EDWARDS, M., and FORREST, J.: Software acceleration using programmable hardware devices, Pmc. IEE Comput. Digit. Tech., 1996, 143, (1), pp. 55-63
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    • Edwards, M.1    Forrest, J.2
  • 14
    • 0033281192 scopus 로고    scopus 로고
    • Partitioning and pipelining for performance-constrained hardware/software systems
    • BAKSHI, S., and GAJSKI, D.: Partitioning and pipelining for performance-constrained hardware/software systems, IEEE Trans. VLSI Syst., 1999, 7, (4), pp. 419-432
    • (1999) IEEE Trans. VLSI Syst. , vol.7 , Issue.4 , pp. 419-432
    • Bakshi, S.1    Gajski, D.2
  • 15
    • 0032097108 scopus 로고    scopus 로고
    • Improving functional density using run-time circuit reconfiguration
    • WIRTHL1N, M.J., and HUTCHINGS, B.L.: Improving functional density using run-time circuit reconfiguration, IEEE Trans. VLSI Syst., 1998, 6, (2), pp. 247-256
    • (1998) IEEE Trans. VLSI Syst. , vol.6 , Issue.2 , pp. 247-256
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    • Frontier Design, Melbourne, FL, USA
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  • 20
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    • Efficient program tracing
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  • 23
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.