Hardware-efficient DFT designs with cyclic convolution and subexpression sharing

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 47, Issue 9, 2000, Pages 886-892

  Chang, Tian Sheuan ^a,b   Guo, Jiun In ^a   Jen, Chein Wei ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL UNITED UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC;

DISCRETE FOURIER TRANSFORMS (DFT);

FOURIER TRANSFORMS;

EID: 0034269323     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.868456     Document Type: Article

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