On the Real-Time Computation of DFT and DCT through Systolic Architectures

IEEE Transactions on Signal Processing

Volumn 42, Issue 4, 1994, Pages 988-991

  Murthy, N Rama ^a   Swamy, M N S ^a  

^a Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CIRCUIT THEORY; SIGNAL PROCESSING;

DCT PROCESSORS; DFT PROCESSORS; SYSTOLIC ARCHITECTURES;

VLSI CIRCUITS;

EID: 0028410099     PISSN: 1053587X     EISSN: 19410476     Source Type: Journal    
DOI: 10.1109/78.285671     Document Type: Article

References (6)

1. H. T. Kung, “Special-purpose devices for signal and image processing: An opportunity in very large scale integration (VLSI),” in Proc. SPIE Real-Time Signal Processing-III 1980, pp. 76–84, vol. 241.
2. M. A. Bayoumi, G. A. Jullien, and W. C. Miller, “A VLSI array for computing the DFT based on RNS,” Proc. ICASSP 86, (Tokyo), pp. 2147–2150.
3. L. W. Chang and M. Y. Chen, “A new systolic array for discrete Fourier transform,” IEEE Trans. Acoust. Speech Signal Processing, vol. 36, pp. 1665–1666, Oct. 1988.
4. N. I. Cho and S. U. Lee, “DCT algorithms for VLSI parallel implementations,” IEEE Trans. Acoust. Speech Signal Processing, vol. 38, pp. 121–127, Jan. 1990.
5. C. Chakrabarti and J. Ja‘Ja’, “Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decomposition,” IEEE Trans. Comput., vol. C-39, pp. 1359–1368, Nov. 1990.
6. L. W. Chang and M. C. Wu, “A unified systolic array for discrete cosine transform and sine transforms,” IEEE Trans. Signal Processing, vol. 39, pp. 192–194, Jan. 1991.