The Efficient Memory-Based VLSI Array Designs For DFT and DCT

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 39, Issue 10, 1992, Pages 723-733

  Guo, Jiun In ^a   Liu, Chi Min ^a   Jen, Chein Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

FOURIER TRANSFORMS; ROM;

CYCLIC CONVOLUTION FORMS; DISCRETE COSINE TRANSFORM (DCT); DISCRETE FOURIER TRANSFORM (DFT); MEMORY-BASED VLSI ARRAY DESIGN; SYSTOLIC ARRAYS;

VLSI CIRCUITS;

EID: 0026929637     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.199898     Document Type: Article

References (31)

1. H. T.Kung, “Why systolic architectures?” Comput. Mag., vol. 15, pp. 37–45, Jan. 1982.
2. H. T.Kung, “Special purpose devices for signal and image processing: An opportunity in very large scale integration (VLSI),” Proc. SPIEL, vol. 241, pp. 76–84, 1980.
3. J. A. Beraldin, T. Aboulnasr, and W. Steenaart, “Efficient one-dimensional systolic array realization of discrete Fourier transform,” IEEE Trans. Circuits Syst., vol. 36, pp. 95–100, Jan. 1989.
4. L. W. Chang and M. Y. Chen, “A new systolic array for discrete Fourier transform,”IEEE Trans. Acoust. Speech, Signal Processing, vol. 36, pp. 1665–1667, Oct. 1988.
5. M. A. Bayoumi, G. A. Jullien, and W. C. Miller, “A VLSI array for computing the DFT based on RNS,” Proc. ICASSP, pp. 2147–2150, 1986.
6. T. E. Curtis and J. T. Wickenden, “Hardware-based Fourier transforms: Algorithms and architectures,” Proc. Inst. Elec. Eng., vol. 130, Pt.F, pp. 423–432, Aug. 1983.
7. C. D. Thompson, “Fourier transforms in VLSI,” IEEE Trans. Computers, vol. C-32, pp. 1047–1057, Nov. 1983.
8. C. M. Liu and C. W. Jen, “A new systolic array algorithm for discrete Fourier transform,” in Proc. ISCAS, pp. 2212–2215, 1991.
9. U. Totzek and F. Matthiesen, “Two-dimensional discrete cosine transform with linear systolic arrays,” in Proc. Int. Conf. Systolic Arrays, pp. 388–397, 1989.
10. N. I. Cho and S. U. Lee, “DCT algorithms for VLSI parallel implementations,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 38, pp. 121–127, Jan. 1990.
11. L. W. Chang and M. C. Wu, “A unified systolic array for discrete cosine and sine transforms,” IEEE Trans. Signal Processing, vol. 39, pp. 192–194, Jan. 1991.
12. C. Chakrabarti and J. JaJa, “Systolic architectures for the computation of the discrete Hartley and the discrete cosine transforms based on prime factor decomposition,” IEEE Trans. Computers, vol. 39, pp. 1359–1368, Nov. 1990.
13. M. H. Lee, “On computing 2-D systolic algorithm for Discrete Cosine Transform,” IEEE Trans. Circuits Syst., vol. 37, pp. 1321–1323, Oct. 1990.
14. J. I. Guo, C. M. Liu, and C. W. Jen, “New systolic arrays for prime length discrete cosine transform,” IEEE Workshop on Visual Signal Processing and Communications, pp. 67–70, June 1991.
15. A. L. Fisher and H. T. Kung, “Special-purpose VLSI architectures: General discussions and a case study,” in VLSI and Modem Signal Processing Ed. by S. Y. Kung et al. Englewood Cliffs, NJ: Prentice-Hall, 1985, ch. 8, pp. 154–169.
16. G.-K. Ma and F. J. Taylor, “Multiplier policies for digital signal processing,” IEEE ASSP Mag., pp. 6–20, Jan. 1990.
17. C. M. Rader, “Discrete Fourier transforms when the number of data samples is prime,” Proc. IEEE, vol. 56, pp. 1107–1108, 1968.
18. C. W. Jen and H. Y. Hsu, “The design of a systolic array with tags input,” in Proc. ISCAS, pp. 2263–2266, 1988.
19. N. Demassieux, G. Concordel, J.-P. Durandeau, and F. Jutand, “An optimized VLSI architecture for a multiformat discrete cosine transform,” in Proc. ICASSP, pp. 547–550, 1987.
20. M. T. Sun, T. C. Chen, and A. M. Gottlieb, “VLSI implementation of a 16 × 16 discrete cosine transform,” IEEE Trans. Circuits Syst., vol. 36, pp. 610–617, Apr. 1989.
21. K. K. Chau, I.-F. Wang, and C. L. Eldridge, “VLSI implementation of a 2-D DCT in a compiler,” Proc. ICASSP, pp. 1233–1236, 1991.
22. F. Jutand, Z. J. Mou, and N. Demassieux, “DCT architectures for HDTV,” in Proc. ISCAS, pp. 196–199, 1991.
23. B. Sikstrom, L. Wanhammar, M. Afghahi, and J. Pencz, “A high speed 2-D discrete cosine transform chip,” Integration: The VLSI Journal, vol. 5, pp. 159–169, June 1987.
24. M. T. Sun, T. C. Chen, A. Gottlieb, L. Wu, and M. L. Liou, “A 16 × 16 discrete cosine transform chip,” Visual Commun. and Image Process. II, SPIE, vol. 845, pp. 13–18, Oct. 1987.
25. M. T. Sun, L. Wu, and M. L. Liou, “A concurrent architecture for VLSI implementation of discrete cosine transform,” IEEE Trans. Circuits System, vol. CAS-34, pp. 992–994, Aug. 1987.
26. T. C. Chen, A. Gottlieb, and M. T. Sun, “VLSI implementation of a 16 × 16 DCT,” in Proc. ICASSP, pp. 1973–1976, Apr. 1988.
27. A. M. Gottlieb, M. T. Sun, and T. C. Chen, “A video rate 16 × 16 discrete cosine transform IC,” in Proc. IEEE 1988 Custom Integrated Circuits Conf., pp. 8.3.1-8.3.4, May 1988.
28. J. C. Carlach, P. Penard, and J. L. Sicre, “TCAD: A 27 MHz 8 ×8 discrete cosine transform chip, in Proc. ICASSP, pp. 2429–2432, May 1989.
29. I. Defilippis, U. Sjostrom, M. Ansorge, and F. Pellandini, “A two dimensional 16 point discrete cosine transform chip for real-time video applications,” Douzieme colloque sur le traitement du signal et des images, pp. 813–816, June 1989.
30. J. S. Ward et al., “Figures of merit for VLSI implementation of digital signal processing algorithms,” Proc. Inst. Elec. Eng., vol. 131, pt.F, pp. 64–70, Feb. 1984.
31. H. C. Reeve, III, and J. R. Lim, “Reduction of blocking effect in image coding, in Proc. ICASSP, pp. 1212–1215, 1983.