-
2
-
-
0021477994
-
-
468-473, Aug. 1984.
-
H. J. M. Veendrick, ;Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,; IEEE J. Solid-State Circuits, vol. SC-19, pp. 468-473, Aug. 1984.
-
;Short-circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits,; IEEE J. Solid-State Circuits, Vol. SC-19, Pp.
-
-
Veendrick, H.J.M.1
-
3
-
-
84937744575
-
-
285-289, Sept. 1968.
-
H. Shichman and D. A. Hodges, ;Modeling and simulation of insulated-gate field-effect transistor switching circuits,; IEEE J. Solid-State Circuits, vol. SC-3, pp. 285-289, Sept. 1968.
-
;Modeling and Simulation of Insulated-gate Field-effect Transistor Switching Circuits,; IEEE J. Solid-State Circuits, Vol. SC-3, Pp.
-
-
Shichman, H.1
Hodges, D.A.2
-
4
-
-
0023315137
-
-
270-281, Mar. 1987.
-
N. Hedenstierna and K. O. Jeppson, ;CMOS circuit speed and buffer optimization,; IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 270-281, Mar. 1987.
-
;CMOS Circuit Speed and Buffer Optimization,; IEEE Trans. Computer-Aided Design, Vol. CAD-6, Pp.
-
-
Hedenstierna, N.1
Jeppson, K.O.2
-
5
-
-
11544321565
-
-
12, pp. 180-181, Jan. 1993.
-
;Comments on 'A module generator for optimized CMOS buffers',; IEEE Trans. Computer-Aided Design, vol. 12, pp. 180-181, Jan. 1993.
-
Vol.
-
-
-
7
-
-
0032025472
-
-
45, pp. 259-270, Mar. 1998.
-
L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, ;Propagation delay and short-circuit power dissipation modeling of the CMOS inverter,; IEEE Trans. Circuits Syst. I, vol. 45, pp. 259-270, Mar. 1998.
-
S. Nikolaidis, and O. Koufopavlou, ;Propagation Delay and Short-circuit Power Dissipation Modeling of the CMOS Inverter,; IEEE Trans. Circuits Syst. I, Vol.
-
-
Bisdounis, L.1
-
8
-
-
0029194991
-
-
1995, pp. 129-134.
-
S. Turgis, N. Azemard, and D. Auvergne, ;Explicit evaluation of short-circuit power dissipation for CMOS logic structures,; in Proc. Int. Symp. Low-Power Design, Apr. 1995, pp. 129-134.
-
N. Azemard, and D. Auvergne, ;Explicit Evaluation of Short-circuit Power Dissipation for CMOS Logic Structures,; in Proc. Int. Symp. Low-Power Design, Apr.
-
-
Turgis, S.1
-
9
-
-
0025415048
-
-
25, pp. 584-594, Apr. 1990.
-
T. Sakurai and A. R. Newton, ;Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,; IEEE J. Solid-State Circuits, vol. 25, pp. 584-594, Apr. 1990.
-
;Alpha-power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,; IEEE J. Solid-State Circuits, Vol.
-
-
Sakurai, T.1
Newton, A.R.2
-
11
-
-
0028550055
-
-
41, pp. 762-765, Nov. 1994.
-
S. R. Vemuru and N. Scheinberg, ;Short-circuit power dissipation estimation for CMOS logic gates,; IEEE Trans. Circuits Syst. I, vol. 41, pp. 762-765, Nov. 1994.
-
;Short-circuit Power Dissipation Estimation for CMOS Logic Gates,; IEEE Trans. Circuits Syst. I, Vol.
-
-
Vemuru, S.R.1
Scheinberg, N.2
-
12
-
-
0030102883
-
-
1996, pp. 304-311.
-
A. Hirata, H. Onodera, and K. Tamaru, ;Estimation of short-circuit power dissipation for static CMOS gates,; in IEICE Trans. Fundament. Electron., Commun. Comput. Sci., vol. E79-A, Mar. 1996, pp. 304-311.
-
H. Onodera, and K. Tamaru, ;Estimation of Short-circuit Power Dissipation for Static CMOS Gates,; in IEICE Trans. Fundament. Electron., Commun. Comput. Sci., Vol. E79-A, Mar.
-
-
Hirata, A.1
-
13
-
-
0032202465
-
-
17, pp. 1090-1098, Nov. 1998.
-
S. Turgis and D. Auvergne, ;A novel macromodel for power estimation in CMOS structures,; IEEE Trans. Comput.-Aided Design, vol. 17, pp. 1090-1098, Nov. 1998.
-
;A Novel Macromodel for Power Estimation in CMOS Structures,; IEEE Trans. Comput.-Aided Design, Vol.
-
-
Turgis, S.1
Auvergne, D.2
-
16
-
-
33749952466
-
-
1996, pp. 265-274.
-
J. M. Daga, S. Turgis, and D. Auvergne, ;Design oriented standard cell delay modeling,; in Proc. Int. Wkshp. Power Timing Modeling, Optimiz. Simulat., Sept. 1996, pp. 265-274.
-
S. Turgis, and D. Auvergne, ;Design Oriented Standard Cell Delay Modeling,; in Proc. Int. Wkshp. Power Timing Modeling, Optimiz. Simulat., Sept.
-
-
Daga, J.M.1
-
17
-
-
0032649954
-
-
34, pp. 42-55, Jan. 1999.
-
J. M. Daga and D. Auvergne, ;A comprehensive delay macro modeling for submicrometer CMOS logics,; IEEE J. Solid-State Circuits, vol. 34, pp. 42-55, Jan. 1999.
-
;A Comprehensive Delay Macro Modeling for Submicrometer CMOS Logics,; IEEE J. Solid-State Circuits, Vol.
-
-
Daga, J.M.1
Auvergne, D.2
-
18
-
-
0029714804
-
-
1996, pp. 189-192.
-
L. Bisdounis, O. Koufopavlou, and S. Nikolaidis, ;Accurate evaluation of the CMOS short-circuit power dissipation for short-channel devices,; in P roc. IEEE Int. Symp. Low-Power Electron. Design, Aug. 1996, pp. 189-192.
-
O. Koufopavlou, and S. Nikolaidis, ;Accurate Evaluation of the CMOS Short-circuit Power Dissipation for Short-channel Devices,; in P Roc. IEEE Int. Symp. Low-Power Electron. Design, Aug.
-
-
Bisdounis, L.1
-
19
-
-
0028448788
-
-
29, pp. 663-670, June 1994.
-
D. Liu and C. Svensson, ;Power consumption estimation in CMOS VLSI chips,; IEEE J. Solid-State Circuits, vol. 29, pp. 663-670, June 1994.
-
;Power Consumption Estimation in CMOS VLSI Chips,; IEEE J. Solid-State Circuits, Vol.
-
-
Liu, D.1
Svensson, C.2
-
20
-
-
0028517487
-
-
13, pp. 1271-1279, Oct. 1994.
-
A. Nabavi-Lishi and N. C. Rumin, ;Inverter models of CMOS gates for supply current and delay evaluation,; IEEE Trans. Comput.-Aided Design, vol. 13, pp. 1271-1279, Oct. 1994.
-
;Inverter Models of CMOS Gates for Supply Current and Delay Evaluation,; IEEE Trans. Comput.-Aided Design, Vol.
-
-
Nabavi-Lishi, A.1
Rumin, N.C.2
-
21
-
-
33749913039
-
-
1995, pp. 125-169.
-
J. T. Kong and D. Overhauser, ;XQXQXQ,; in Digital Timing Macromodeling for VLSI Design Verification. Norwell, MA: Kluwer Academic, 1995, pp. 125-169.
-
;XQXQXQ,; in Digital Timing Macromodeling for VLSI Design Verification. Norwell, MA: Kluwer Academic
-
-
Kong, J.T.1
Overhauser, D.2
-
22
-
-
0031630137
-
-
6, June 1998, pp. 342-345.
-
L. Bisdounis and O. Koufopavlou, ;Modeling the dynamic behavior of series-connected MOSFET's for delay analysis of multiple-input CMOS gates,; in Proc. IEEE Int. Symp. Circuits Syst., vol. 6, June 1998, pp. 342-345.
-
;Modeling the Dynamic Behavior of Series-connected MOSFET's for Delay Analysis of Multiple-input CMOS Gates,; in Proc. IEEE Int. Symp. Circuits Syst., Vol.
-
-
Bisdounis, L.1
Koufopavlou, O.2
-
24
-
-
0032002404
-
-
33, pp. 302-306, Feb. 1998.
-
L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, ;Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices,; IEEE J. Solid-State Circuits, vol. 33, pp. 302-306, Feb. 1998.
-
S. Nikolaidis, and O. Koufopavlou, ;Analytical Transient Response and Propagation Delay Evaluation of the CMOS Inverter for Short-channel Devices,; IEEE J. Solid-State Circuits, Vol.
-
-
Bisdounis, L.1
-
25
-
-
84893757887
-
-
1998, pp. 2-6.
-
A. Chatzigeorgiou and S. Nikolaidis, ;Collapsing the transistor chain to an effective single equivalent transistor,; in Proc. IEEE Design, Automa. Test Eur., Feb. 1998, pp. 2-6.
-
;Collapsing the Transistor Chain to an Effective Single Equivalent Transistor,; in Proc. IEEE Design, Automa. Test Eur., Feb.
-
-
Chatzigeorgiou, A.1
Nikolaidis, S.2
-
26
-
-
0024737975
-
-
8, pp. 1027-1032, Sept. 1989.
-
Y. H. Jun, K. Jun, and S. B. Park, ;An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation,; IEEE Trans. Comput.-Aided Design, vol. 8, pp. 1027-1032, Sept. 1989.
-
K. Jun, and S. B. Park, ;An Accurate and Efficient Delay Time Modeling for MOS Logic Circuits Using Polynomial Approximation,; IEEE Trans. Comput.-Aided Design, Vol.
-
-
Jun, Y.H.1
-
27
-
-
0000541151
-
-
889-891, Oct. 1986.
-
S. M. Kang, ;Accurate simulation of power dissipation in VLSI circuits,; IEEE J. Solid-State Circuits, vol. SC-21, pp. 889-891, Oct. 1986.
-
;Accurate Simulation of Power Dissipation in VLSI Circuits,; IEEE J. Solid-State Circuits, Vol. SC-21, Pp.
-
-
Kang, S.M.1
-
28
-
-
0032023148
-
-
1998, pp. 462-469.
-
A. Hirata, H. Onodera, and K. Tamaru, ;Analytical formulas of output waveform and short-circuit power dissipation for static CMOS gates driving a CRC π load,; in IEICE Trans. Fundament. Electron., Commun. Comput. Sci., vol. E81-A, Mar. 1998, pp. 462-469.
-
H. Onodera, and K. Tamaru, ;Analytical Formulas of Output Waveform and Short-circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load,; in IEICE Trans. Fundament. Electron., Commun. Comput. Sci., Vol. E81-A, Mar.
-
-
Hirata, A.1
-
29
-
-
0031234331
-
-
14, pp. 29-39, Jan. 1997.
-
V. Alder and E. G. Friedman, ;Delay and power expressions for a CMOS inverter driving a resistive-capacitive load,; Analog Integral. Circuits Signal Processing J., vol. 14, pp. 29-39, Jan. 1997.
-
;Delay and Power Expressions for a CMOS Inverter Driving a Resistive-capacitive Load,; Analog Integral. Circuits Signal Processing J., Vol.
-
-
Alder, V.1
Friedman, E.G.2
-
30
-
-
0028756124
-
-
13, pp. 1526-1535, Dec. 1994.
-
J. Qian, S. Pullela, and L. Pillage, ;Modeling the 'effective capacitance' for the RC interconnect of CMOS gates,; IEEE Trans. Comput.-Aided Design, vol. 13, pp. 1526-1535, Dec. 1994.
-
S. Pullela, and L. Pillage, ;Modeling the 'Effective Capacitance' for the RC Interconnect of CMOS Gates,; IEEE Trans. Comput.-Aided Design, Vol.
-
-
Qian, J.1
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