Short-Circuit Power Dissipation Estimation for CMOS Logic Gates

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 41, Issue 11, 1994, Pages 762-765

  Vemuru, Srinivasa R ^a   Scheinberg, Norman ^a  

^a CITY COLLEGE OF NEW YORK   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC LOSSES; ELECTRICITY; ESTIMATION; LOGIC GATES; MOSFET DEVICES; SHORT CIRCUIT CURRENTS; VLSI CIRCUITS;

ALPHA POWER LAW MODEL; SHORT CIRCUIT POWER DISSIPATION; SOFTWARE PACKAGE SPICE; VELOCITY SATURATION EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 0028550055     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.331533     Document Type: Article

References (10)

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