Estimation of Short-Circuit Power Dissipation for Static CMOS Gates

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E79-A, Issue 3, 1996, Pages 304-310

  Hirata, Akio ^a   Onodera, Hidetoshi ^a   Tamaru, Keikichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

Low power design; Power estimation; Short circuit current; Short circuit power dissipation; Simulation of power dissipation

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ERRORS; ESTIMATION; LEAKAGE CURRENTS; LOGIC GATES; PIECEWISE LINEAR TECHNIQUES; SHORT CIRCUIT CURRENTS;

CURRENT FLOW; PIECEWISE LINEAR FUNCTION; POWER DISSIPATION; POWER ESTIMATION; STATIC LOGIC GATES;

ELECTRIC LOSSES;

EID: 0030102883     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

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