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Volumn 13, Issue 10, 1994, Pages 1271-1279

Inverter Models of CMOS Gates for Supply Current and Delay Evaluation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC WAVEFORMS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS;

EID: 0028517487     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.317470     Document Type: Article
Times cited : (81)

References (13)
  • 2
    • 84939363898 scopus 로고
    • Delay and Current Evaluation in CMOS Circuits
    • McGill University, June
    • A. Nabavi-Lishi, “Delay and Current Evaluation in CMOS Circuits,” Ph.D. Dissertation, McGill University, June 1993.
    • (1993) Ph.D. Dissertation
    • Nabavi-Lishi, A.1
  • 3
    • 0026827836 scopus 로고
    • Simultaneous delay and maximum current calculation in CMOS gates
    • Mar.
    • A. Nabavi-Lishi and N. C. Rumin, “Simultaneous delay and maximum current calculation in CMOS gates,” IEE Electronics Letters, vol. 28, no. 7, 682–684, Mar. 1992.
    • (1992) IEE Electronics Letters , vol.7 , pp. 682-684
    • Nabavi-Lishi, A.1    Rumin, N.C.2
  • 4
    • 0003984119 scopus 로고
    • 119001, Meta-Software, Inc.
    • HSPICE Users Manual, 119001, Meta-Software, Inc., 1990.
    • (1990) HSPICE Users Manual
  • 5
    • 0025439702 scopus 로고
    • Estimation of maximum currents in MOS IC logic circuits
    • June
    • S. Chowdhury and J. S. Barkatullah, “Estimation of maximum currents in MOS IC logic circuits,” IEEE Trans. Computer-Aided Design, vol. 9, no. 6, pp. 642–654, June 1990.
    • (1990) IEEE Trans. Computer-Aided Design , vol.9 , Issue.6 , pp. 642-654
    • Chowdhury, S.1    Barkatullah, J.S.2
  • 6
    • 0024737975 scopus 로고
    • An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation
    • Sept.
    • Young-Hyun Jun, KI Jun, and Song-Bai Park, “An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation,” IEEE Trans. Computer-Aided Design, vol. 8, no. 9, pp. 1027–1032, Sept. 1989.
    • (1989) IEEE Trans. Computer-Aided Design , vol.8 , Issue.9 , pp. 1027-1032
    • Jun, Y.H.1    Jun, K.2    Park, S.B.3
  • 9
    • 0026106011 scopus 로고
    • Delay analysis of series-connected MOSFET circuits
    • Feb.
    • T. Sakurai and A. R. Newton, “Delay analysis of series-connected MOSFET circuits,” IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 122–130, Feb. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.2 , pp. 122-130
    • Sakurai, T.1    Newton, A.R.2
  • 10
    • 0021477994 scopus 로고
    • Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
    • Aug.
    • H. J. M. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. SC-19, no. 4, pp. 468–473, Aug. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SC-19 , Issue.4 , pp. 468-473
    • Veendrick, H.J.M.1
  • 12
    • 0025415048 scopus 로고
    • Alpha-Power law MOSFET model and its applications to CMOS inverter delay and other formulas
    • Apr.
    • T. Sakurai and A. R. Newton, “Alpha-Power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584–593, Apr. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , Issue.2 , pp. 584-593
    • Sakurai, T.1    Newton, A.R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.