A dual body SOI structure for mixed analog-digital mode circuits

IEEE Transactions on Electron Devices

Volumn 47, Issue 8, 2000, Pages 1617-1623

  Lee, Hyeokjae ^b   Lee, Jong Ho ^a,c   Park, Young June ^a,b   Min, Hong Shick ^b  

^a IEEE

^b Seoul National University   (South Korea)

^c Wonkwang University   (South Korea)

Author keywords

Floating body effect; Fully depleted MOSFET's; Mixed analog digital mode circuit; Partially depleted MOSFET's; SOI noise

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; MOSFET DEVICES; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

MIXED ANALOG-DIGITAL MODE CIRCUITS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0034246848     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.853039     Document Type: Article

References (18)

1. H. Lee, J. H. Lee, Y. J. Park, and H. S. Min, "A new SOI structure for mixed mode IC's and its body related characteristics," in Proc. IEEE Int. SOI Conf., 1998, pp. 63-64.
2. D. Sinitsky et al., "AC output conductance of SOI MOSFET's and impact on analog applications," IEEE Electron Device Lett., vol. 18, pp. 36-38, Feb. 1997.
3. M. Yoshimi et al., "Advantage of low voltage application and issues to be solved in SOI technology," in Proc. IEEE Int. SOI Conf., 1996, pp. 4-5.
4. C.-T. Chuang, P.-F. Lu, and C. J. Anderson, "SOI for digital CMOS VLSI: Design considerations and advances," Proc. IEEE, vol. 86, pp. 689-720, Aug. 1998.
5. C. Hu, "SOI and device scaling," in Proc. IEEE Int. SOI Conf., 1998, pp. 1-4.
6. Y. Taur, "The incredible shrinking transistor," IEEE Spectrum, vol. 36, pp. 25-29, July 1999.
7. V. H. C. Chen and J. C. S. Woo, "New approach to implement 0.1 μm MOSFET on the thin-film SOI substrate," in IEDM Tech. Dig., 1994, pp. 657-660.
8. M. Horiuchi and M. Tamura, "BESS a source structure that full suppress the floating body effect," in IEDM Tech. Dig., 1996, pp. 121-124.
9. E. P. V. Ploeg et al., "Elimination of bipolar introduced breakdown in full-depleted SOI MOSFETs," in IEDM Tech. Dig., 1992, pp. 337-340.
10. M. Horiuchi, "A new dynamic threshold SOI device having an embeded resistor and a merged body-bias-control transistor," in IEDM Tech. Dig., 1998, pp. 419-423.
11. W. Chen et al., "Suppression of the SOI floating-body effect by linked-body device structure," in Symp. VLSI Technology Tech. Dig., 1996, pp. 92-93.
12. Y.-H. Koh, J.-H. Choi, M.-H. Nam, and J.-W. Yang, "Body-contacted SOI MOSFET structure with fully bulk CMOS comparable layout and process," IEEE Electron Device Lett., vol. 18, pp. 102-104, Mar. 1997.
13. M. Chan et al., "Recessed-channel structure for fabricating ultra thin SOI MOSFET with low series resistance," IEEE Electron Device Lett., vol. 15, pp. 22-24, Jan. 1994.
14. T. Nishihara, K. Tokunaga, and K. Kobayashi, "A 0.5 μm isolation technology using advanced poly silicon pad LOCOS," in IEDM Tech. Dig., 1988, pp. 100-103.
15. O. Faynot and B. Giffard, "High performance ultrathin SOI MOSFET's obtained by localized oxidation," IEEE Electron Device Lett., vol. 15, pp. 175-177, May 1994.
16. M. Chan et al., "Comparative study of fully depleted body and body ground non fully depleted SOI MOSFET's for high performance analog and mixed signal circuits," IEEE Trans. Electron Devices, vol. 42, pp. 1975-1981, Nov. 1995.
17. ATLAS User's Manual Device Simulation Software ver. 1.5.0, Silvaco Int., Santa Clara, CA, 1997.
18. D. Yachou, J. Gautier, and C. Raynaud, "Self-heating effect on static and dynamic SOI operation," in Proc. ESSDERC, 1993, pp. 695-698.