Body-contacted SOI MOSFET structure with fully bulk CMOS compatible layout and process

IEEE Electron Device Letters

Volumn 18, Issue 3, 1997, Pages 102-104

  Koh, Yo Hwan ^a,b   Choi, Jin Hyeok ^a   Nam, Myung Hee ^a   Yang, Ji Woon ^a  

^a Hynix Semiconductor Inc   (South Korea)

^b IEEE   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENT MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; OXIDES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY; THIN FILMS; VOLTAGE MEASUREMENT;

DRAIN CURRENT; DRAIN INDUCED BARRIER LOWERING CHARACTERISATION; DRAIN VOLTAGE; TUNGSTEN POLYCIDE;

MOSFET DEVICES;

EID: 0031102986     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.556094     Document Type: Article

References (6)

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2. D. Suh and J. G. Fossum, "A physical charge-based model for nonfully depleted SOI MOSFET's and its use in assessing floating-body effects in SOI CMOS circuits," IEEE Trans. Electron Devices, vol. 42, pp. 728-737, Apr. 1995.
3. M. Yoshimi, M. Terauchi, A. Murakoshi, M. Takahashi, K. Matsuzawa, N. Shigyo, and Y. Ushiku, "Technology trends of silicon-oninsulator - its advantages and problems to be solved," in IEDM Tech. Dig., 1994, pp. 429-432.
4. E. P. Ver Ploeg, T. Watanabe, N. A. Kistler, J. C. S. Woo, and J. D. Plummer, "Elimination of bipolar induced breakdown in fully-depleted SOI MOSFET's," in IEDM Tech. Dig., 1992, pp. 337-340.
5. H. F. Wei, N. M. Kalkhoran, F. Namavar, and J. E. Chung, "Improvement of breakdown voltage and off-state leakage in Ge-implanted SOI n-MOSFET's," in IEDM Tech. Dig., 1993, pp. 739-742,
6. T. Iwamatsu, Y. Yamaguchi, Y. Inoue, and T. Nishimura, "CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation," IEEE Trans. Electron Devices, vol. 42, pp. 1934-1939, Nov. 1995.