CMOS shallow-trench-isolation to 50-nm channel widths

IEEE Transactions on Electron Devices

Volumn 47, Issue 6, 2000, Pages 1175-1182

  Vandervoorn, Peter ^a,b   Gan, Dong ^a,b   Peter Krusius, J ^a,b  

^a INTEL CORPORATION   (United States)

^b School of Operations Research and Industrial Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC BREAKDOWN; FINITE ELEMENT METHOD; MOSFET DEVICES; REACTIVE ION ETCHING; SEMICONDUCTING BORON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; THREE DIMENSIONAL; THRESHOLD VOLTAGE; TRANSISTORS;

CHANNEL EDGE EFFECTS; CHANNEL WIDTHS; SHALLOW TRENCH ISOLATION; THRESHOLD VOLTAGE ROLL-OFF; TRENCH WIDTHS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0033731725     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.842959     Document Type: Article

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