Trench isolation with Del (nabla)-shaped buried oxide for 256 mega-bit DRAMs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 275-278

  Shibahara, K ^a   Fujimoto, Y ^a   Hamada, M ^a   Iwao, S ^a   Tokashiki, K ^a   Kunio, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BURIED OXIDES; FABRICATION PROCESS; ISOLATION CHARACTERISTICS; JUNCTION CAPACITANCES; TRENCH ISOLATION; TRENCH SIDEWALLS;

ELECTRON DEVICES;

EID: 33747184771     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307359     Document Type: Conference Paper

References (7)

1. T. Iizuka, K. Y. Chiu and J. L. Moll, "Double threshold MOSFETs in bird's-beak free structure. ", IEDM Technical Digest, pp. 380, 1981.
2. T. Nishizaka, K. Hashimoto, T. Kohno, K. Tasaka, et al., "32Mbit very high density mask ROM", NEC Res. & Develop., vol. 32, pp. 48, 1991.
3. M. Aoki H. Takato S. Samata M. Numano et al., "Quartermicron selective-epitaxial-silicon refilled trench(SRT) isolation technology with substrate shield", IEDM Technical Digest, pp. 447, 1991.
4. B. Davari, C. W. Koburger, R. Sculz, J. D. Warnock etal., "A new planarazation technique, using a combination of RIE and chemical mechanical polish(CMP)", IEDM Technical Digest, pp. 61, 1989.
5. T. Gocho, Y. Morita, J. Sato, "Trench isolation technology for 0. 35}lmdevice by bias ECR CVD", 1991 Symposium on VLSI Technology, pp87.
6. K. Ohe, S. Odanaka, K. Moriyama, T. Hori et al., "Narrowwidth effects of shallow trench-isolated CMOS with n+polysilicon gate", IEEE Trans. Electron Devices, Vol. ED-36, pp. 1110, 1989.
7. R. Dang, N. Shigyo, T. Wada, S. Onaga et al., "An analysis of MOSFET's narrow-channel effects", IEEE I CCC Technology Digest, pp. 286, 1982.