Efficient Algorithms for Channel Routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 1, Issue 1, 1982, Pages 25-35

  Yoshimura, Takeshi ^a   Kuh, Ernest S ^b  

^a NEC CORPORATION   (Japan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, LSI - COMPUTER AIDED DESIGN; MATHEMATICAL TECHNIQUES;

CHANNEL ROUTING; NETS; TWO-LAYER CHANNEL;

COMPUTER PROGRAMMING;

EID: 0019923262     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1982.1269993     Document Type: Article

References (8)

1. A. Hashimoto and S. Stevens, “Wire routing by optimizing channel assignment within large apertures,” in Proc. 8th Design Automation Workshop, pp. 155-169, 1971.
2. D. N. Deutsch, “A dogleg channel router,” in Proc. 13th Design Automation Conf., 1976.
3. G. Persky, D. N. Deustch, and D. G. Schweikert, “LTX-A minicomputer-based system for automatic LSI layout,” J. Design Automation and Fault-Tolerant Computing, pp. 217-255, May 1977.
4. “LTX-A system for the directed automation design of LSI circuits,” in Proc. 13th Design Automation Conf., 1976.
5. B. W. Kernighan, D.G. Schweikert, and G. Persky, “An optimum channel-routing algorithm for polycell layouts of integrated circuits,” in Proc. 10th Design Automation Workshop, pp. 50-59, 1973.
6. T. Ohtsuki, H. Mori, E. S. Kuh, T. Kashiwabara, and T. Fujisawa, “One-dimensional logic gate assignment and interval graphs,” IEEE Trans. Circuits Syst., vol. CAS-26, pp. 675-684, Sept. 1979.
7. C. G. Lekerkerker and J. Ch. Boland, “Representation of a finite graph by a set of intervals on the real line,” Fund. Math., vol. 51, pp. 45-64, 1962.
8. W. Donath, private communication.