Chip Substrate Resistance Modeling Technique for Integrated Circuit Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 3, Issue 2, 1984, Pages 126-134

  Johnson, Thomas A ^a   Knepper, Ronald W ^a   Marcello, Victor ^a   Wang, Wen ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC MEASUREMENTS - RESISTANCE; SEMICONDUCTOR DEVICES, BIPOLAR - COMPUTER AIDED DESIGN; TRANSISTORS, FIELD EFFECT - COMPUTER AIDED DESIGN;

CHIP SUBSTRATE RESISTANCE MODEL; STATISTICAL SIMULATION TECHNIQUES;

INTEGRATED CIRCUITS, VLSI;

EID: 0021405731     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1984.1270066     Document Type: Article

References (5)

1. R. W. Knepper, unpublished.
2. W. T. Weeks, A. J. Jimenez, G. W. Mahoney, D. A. Mehta, H. Quassemzadeh, and T. R. Scott, “Algorithms for ASTAP-A network analysis program,” IEEE Trans. Circuit Theory, vol. CT-20, pp. 628–634, Nov. 1973.
3. R. W. Knepper and P. T. Liu, unpublished.
4. N. Balbanian, T. A. Bicker, Electrical Network Theory. New York: Wiley, 1969.
5. F. M. Smits, “Measurement of sheet resistivities with the four-point probe,” Bell Syst. Tech. J., pp. 711–718, May 1958.