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Volumn 26, Issue 1, 1991, Pages 32-40

Optimum Buffer Circuits for Driving Long Uniform Lines

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS - APPLICATIONS;

EID: 0025953236     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.65707     Document Type: Article
Times cited : (103)

References (16)
  • 1
    • 0004263265 scopus 로고    scopus 로고
    • Introduction to VLSI Systems
    • Ed., Reading, MA: Addison-Wesley
    • C. Mead and L. Conway, Eds., Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
    • Mead, C.1    Conway, L.2
  • 2
    • 0020300989 scopus 로고
    • The wire-limited chip
    • Dec.
    • R. W. Keyes, “The wire-limited chip,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1232–1233, Dec. 1982.
    • (1982) IEEE J. Solid-State Circuits , vol.SC-17 , pp. 1232-1233
    • Keyes, R.W.1
  • 3
    • 0000325641 scopus 로고
    • Effect of scaling of interconnections on the time delay of VLSI circuits
    • Apr.
    • K. C. Saraswat and F. Mohammadi, “Effect of scaling of interconnections on the time delay of VLSI circuits,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 275–280, Apr. 1982.
    • (1982) IEEE J. Solid-State Circuits , vol.SC-17 , pp. 275-280
    • Saraswat, K.C.1    Mohammadi, F.2
  • 4
    • 0020116936 scopus 로고
    • Speed limitation due to interconnect time constants in VLSI integrated circuits
    • Apr.
    • A. K. Sinha, J. A. Cooper, and H. J. Levinstein, “Speed limitation due to interconnect time constants in VLSI integrated circuits,” IEEE Electron Device Lett., vol. EDL-3, pp. 90–92, Apr. 1982.
    • (1982) IEEE Electron Device Lett. , vol.EDL-3 , pp. 90-92
    • Sinha, A.K.1    Cooper, J.A.2    Levinstein, H.J.3
  • 5
    • 0003037829 scopus 로고
    • Algorithms for VLSI processor arrays
    • C. Mead and L. Conway, Eds., Reading, MA: Addison-Wesley, Sect. 8.3
    • H. T. Kung and C. E. Leiserson, “Algorithms for VLSI processor arrays,” in Introduction to VLSI Systems, C. Mead and L. Conway, Eds. Reading, MA: Addison-Wesley, 1980, Sect. 8.3.
    • (1980) Introduction to VLSI Systems
    • Kung, H.T.1    Leiserson, C.E.2
  • 7
    • 0020719554 scopus 로고
    • Asynchronous and clocked control structures for VLSI based interconnection networks
    • Mar.
    • D. L. Wann and M. A. Franklin, “Asynchronous and clocked control structures for VLSI based interconnection networks,” IEEE Trans. Computers, vol. C-32, no. 3, pp. 284–293, Mar. 1983.
    • (1983) IEEE Trans. Computers , vol.C-32 , Issue.3 , pp. 284-293
    • Wann, D.L.1    Franklin, M.A.2
  • 8
    • 0016498379 scopus 로고
    • An optimized output stage for MOS integrated circuits
    • Apr.
    • H. C. Lin and L. W. Linholm, “An optimized output stage for MOS integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-10, no. 2, pp. 106–109, Apr. 1975.
    • (1975) IEEE J. Solid-State Circuits , vol.SC-10 , Issue.2 , pp. 106-109
    • Lin, H.C.1    Linholm, L.W.2
  • 9
    • 84922849140 scopus 로고
    • Comments on An optimized output stage for MOS integrated circuits
    • June
    • R. C. Jaeger, “Comments on 'An optimized output stage for MOS integrated circuits,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 185–186, June 1975.
    • (1975) IEEE J. Solid-State Circuits , vol.SC-10 , pp. 185-186
    • Jaeger, R.C.1
  • 10
    • 0022061669 scopus 로고
    • Optimal interconnection circuits for VLSI
    • May
    • H. B. Bakoglu and J. D. Meindl, “Optimal interconnection circuits for VLSI,” IEEE Trans. Electron Devices, vol. ED-32, no. 5, pp. 903–909, May 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , Issue.5 , pp. 903-909
    • Bakoglu, H.B.1    Meindl, J.D.2
  • 12
    • 0020166761 scopus 로고
    • Minimum propagation delays in VLSI
    • Aug.
    • C. Mead and M. Rem, “Minimum propagation delays in VLSI,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 773–775, Aug. 1982.
    • (1982) IEEE J. Solid-State Circuits , vol.SC-17 , pp. 773-775
    • Mead, C.1    Rem, M.2
  • 13
    • 0020595891 scopus 로고
    • CMOS circuit optimization
    • A. Kanuma, “CMOS circuit optimization,” Solid-State Electron., vol. 26, pp. 47–58, 1983.
    • (1983) Solid-State Electron. , vol.26 , pp. 47-58
    • Kanuma, A.1
  • 14
    • 84890245567 scopus 로고    scopus 로고
    • Nonlinear Programming: Theory and Algorithms
    • New York: Wiley
    • M. S. Bazaraa and C. M. Shetty, Nonlinear Programming: Theory and Algorithms. New York: Wiley, 1979.
    • Bazaraa, M.S.1    Shetty, C.M.2
  • 15
  • 16
    • 0021372077 scopus 로고
    • Driving large capacitances in MOS LSI systems
    • Feb.
    • M. Nemes, “Driving large capacitances in MOS LSI systems,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 159–161, Feb. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SC-19 , pp. 159-161
    • Nemes, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.