Algorithms for an Advanced Fault Simulation System in MOTIS

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 6, Issue 2, 1987, Pages 232-240

  Lo, Chi Yuan ^a   Nham, Hao N ^a   Bose, Ajoy K ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUITS, LSI; LOGIC DESIGN;

FAULT SIMULATION; FAULTY GATE; MOTIS SIMULATION;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0023312619     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270267     Document Type: Article

References (13)

1. E. G. Ulrich and T. Baker, “The concurrent simulation of nearly identical digital networks,” in 10th Des. Automat. Workshop Proc., 1973.
2. D. M. Schuler and R. K. Cleghorn, “An efficient method of fault simulation for digital circuits modeled from Boolean gates and memories,” in Proc. 14th Des. Automat. Conf., 1977.
3. M. Abramovici, M. A. Breuer, and K. Kumar, “Concurrent fault simulation and functional level modeling,” in Proc. 14th Des. Automat. Conf., 1977.
4. H. N. Nham and A. K. Bose, “A multiple delay simulator for MOS LSI circuits,” in Proc. 17th Des. Automat. Conf. (Minneapolis, MN), June 23–25, 1980, pp. 610–617.
5. A. K. Bose, P. Kozak, C-Y Lo, H. N. Nham E. Pacas-Skewes, and K. W. Wu, “A fault simulator for MOS LSI circuits,” in Proc. 19th Des. Automat. Conf. (Las Vegas, NV), June 1982.
6. C-Y Lo, H. N. Nham, and A. K. Bose, “A data structure for MOS circuits,” in Proc. 20th Des. Automat. Conf. (Miami Beach, FL), June 27–29 1983, pp. 619–624.
7. C. F. Chen C-Y Lo, H. N. Nham, and P. Subramaniam, “The second generation MOTIS mixed-mode simulator,” in Proc. 21st Des. Automat. Conf., June 1984.
8. S. K. Jain and V. D. Agrawal, “STAFAN: An alternative for fault simulation,” in Proc. 21st Des. Automat. Conf., June 1984.
9. A. V. Aho, J. E. Hopcroft, and J. D. Ullman Data Structures and Algorithms. Reading, MA: Addison-Wesley, 1983.
10. R. E. Bryant and M. D. Schustor, “Fault simulation of MOS digital circuits,” VLSI Design, pp. 24–30, Oct. 1983.
11. H-C Shih, J. T. Rahmeh, and J. A. Abraham, “FAUST: An MOS fault simulator with timing information,” IEEE Trans. Computer-Aided Design, vol. CAD-5, Oct. 1986.
12. R. L. Wadsack, “Fault modeling and logic simulation of CMOS and MOS integrated circuits,” Bell Syst. Tech. J., vol. 57, pp. 1449–1473, May-June 1978.
13. J. Galiay et al., “Physical versus logical fault models MOS LSI circuits: Impact on their testability,” IEEE Trans. Comput., vol. C-29, pp. 527–531, June 1980.