Simulating static and dynamic faults in BIST structures with a FPGA based emulator

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 849 LNCS, Issue , 1994, Pages 240-250

  Wieler, Richard W ^a   Zhang, Zaifu ^a   McLeod, Robert D ^a  

^a UNIVERSITY OF MANITOBA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CIRCUIT SIMULATION; COMPUTER HARDWARE; DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GRADING;

BIST TECHNIQUES; CIRCUIT EMULATION; COMPLEX DESIGNS; DELAY FAULT SIMULATION; DYNAMIC RE-CONFIGURATION; SIGNATURE ANALYSIS; STATIC AND DYNAMIC FAULTS; STATISTICAL INFORMATION;

RECONFIGURABLE HARDWARE;

EID: 21644456414     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-58419-6_94     Document Type: Conference Paper

References (19)

1. A. Krasniewski, and S. Pilarski, Circular Self-Test Path: A Low-Cost BIST Technique for VLSI Circuits, IEEE Transactions on Computer-Aided Design, Vol. 8, pp.425-428, Jan. 1989.
2. S. Pilarski, A. Krasniewski, and T. Kameda, Estimating Testing Effectiveness of the Circular Self-Test Path Technique, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, pp.1301-1317, Oct. 1992.
3. Algotronix Ltd., Configurable Array Logic User Manual, Edinburgh UK, 1991.
4. E. J. McClauskey, Built-in Self-Test Techniques, IEEE Design and Test of Computers, pp.21-36, April 1985.
5. P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
6. V.D. Agrawal, C.R. Kime, and K.K. Saluja, A Tutorial on Built-in Self-Test, Part I, IEEE Design and Test of Computers, pp.73-82, March 1993.
7. V.D. Agrawal, C.R. Kime, and K.K. Saluja, A Tutorial on Built-in Self-Test, Part II, IEEE Design and Test of Computers, pp.69-77, June 1993.
8. Y. Zorian and A. Ivanov, Programmable Space Compaction BIST, Proc. of Int'l Symp. on FTC, pp.340-349, 1993.
9. P.D. Hortensius, R.D. McLeod, W. Pries, D.M. Miller, and H.C. Card, Cellular Automata-Based Pseudorandom Number Generators for Built-in Self-Test, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8, No.8, pp.842-859, Aug. 1989.
10. P.H. Bardell and W.H. McAnney, Self-Testing of Multichip Logic Modules, Proc. of Int'l Test Conference, pp.200-204, 1982.
11. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.
12. D.R. Schertz and G. Metze, A New Representation for Faults in Combinational Digital Circuits, IEEE Transaction on Computers, Vol.21, No.8, Aug. 1972.
13. J.E Chen, C.L. Lee, and W.Z. Shen, Single-Fault Fault-Collapsing Analysis in Sequential Logic Circuits, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, No.12, pp.1559-1568 Dec. 1991.
14. The TTL Data Book for Design Engineers, Texas Instruments, Inc. Dallas, TX, 1981.
15. S.B. Aker and B. Krishnamurty, On the Application of Test Counting to VLSI Testing, pp. 343-359, Chapel Hill Conference on VLSI 1985.
16. J.L.A. Hughes and E.J. McClauskey, Multiple Stuck-at Fault Coverage of Single Stuck-at Fault Test Sets, Proc. of Int’l Test Conference, pp.368-374, 1986.
17. Y. Ievendel and P.R. Menon, Transition Faults in Combinational Circuits: Input Transition Test Generation and Fault Simulation, 16th Int’l Symposium on Fault Tolerant Computing Systems, pp. 278-291, 1986.
18. R. L. Wadsack, Fault Modelling and Logic Simulation of CMOS and MOS Integrated Circuits, Bell System Technical Journal 57(5), pp. 1449-1474, 1978.
19. J.A. Waicukauski, E. Lindbloom, B.R. Rosen, and V. S. Igengar, Transition Fault Simulation, IEEE Design & Test of Computers, pp. 32-38, April 1987.