Method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator

Digest of Papers - International Test Conference

Volumn , Issue , 1988, Pages 102-107

  Hirose, Fumiyasu ^a   Takayama, Koichiro ^a   Kawato, Nobuaki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PATTERN RECOGNITION;

TEST-GENERATION CIRCUIT; ULTRAHIGH-SPEED SIMULATOR;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0024124839     PISSN: 07431686     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)