Core logic simultaneous switching noise measurements on a 500 MHz CMOS chip on a CBGA SCM

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 605-609

  Singh, B ^a   Becker, W D ^a   McAllister, M ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NETWORK COMPONENTS; CAPACITANCE MEASUREMENT; CAPACITORS; COMPUTER SIMULATION; FUNCTIONS; LOGIC CIRCUITS; POWER SUPPLY CIRCUITS; SPURIOUS SIGNAL NOISE; SWITCHING THEORY; VOLTAGE MEASUREMENT;

CMOS CHIPS; CORE LOGIC; DECOUPLING CAPACITOR; FREQUENCY OF OPERATION; LOGIC SWITCHING; POWER-SUPPLY NOISE; SIMULTANEOUS SWITCHING NOISE; THIN OXIDES;

COMPUTER CIRCUITS; MICROPROCESSOR CHIPS;

INTERNAL LOGIC SWITCHING; ON CHIP THIN OXIDE DECOUPLING CAPACITORS;

EID: 0031625566     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678757     Document Type: Conference Paper

References (2)

1. W. Becker, B. McCredie, G. Wilkins, A. Iqbal, "Power distribution modeling of high performance first level computer packages, " IEEE 2nd Topical Meeting on Electrical Performance of Electronic Packaging. Oct. 20-22, 1993, pp. 202-205.
2. B. McCredie, W. Becker, "Modeling, Measurement, Simulation of Simultaneous Switching Noise, " IEEE Trans, on Components, Packaging and Manufacturing Technology, Part B, Vol. 19, No 3, pp 461-472, August 1996.