Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 12, 1997, Pages 1514-1521

  Nowick, Steven M ^a   Jha, Niraj K ^a   Cheng, Fu Chiung ^a  

^a Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION; ROBUSTNESS (CONTROL SYSTEMS); TESTING;

ASYNCHRONOUS CIRCUITS;

DELAY CIRCUITS;

EID: 0031365529     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.664232     Document Type: Article

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