Partial scan delay fault testing of asynchronous circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1997, Pages 728-735

  Kishinevsky, Michael ^a   Kondratyev, Alex ^a   Lavagno, Luciano ^a   Saldanha, Alexander ^a   Taubin, Alexander ^a  

^a UNIVERSITY OF AIZU   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; HEURISTIC METHODS; LOGIC DESIGN; VECTORS;

PARTIAL SCAN DELAY FAULT TESTING; TEST PATTERN GENERATION;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0031354152     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)