Critical hazard free test generation for asynchronous circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 203-208

  Khoche, Ajay ^a   Brunvand, Erik ^a  

^a Sunrise Test Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; ALGORITHMS; ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER AIDED NETWORK ANALYSIS; LOGIC CIRCUITS;

AUTOMATIC TEST PATTERN GENERATOR (ATPG); HAZARD FREE TESTS; SELF-TIMED CONTROL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0030651905     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)