Effective excursion detection by defect type grouping in in-line inspection and classification

IEEE Transactions on Semiconductor Manufacturing

Volumn 12, Issue 1, 1999, Pages 3-10

  Shindo, Wataru ^a,b   Wang, Eric H ^c   Akella, Ramakrishna ^a,c   Strojwas, Andrzej J ^a,d   Tomlinson, Wanda ^e   Bartholomew, Richard ^e  

^a IEEE   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

^c STANFORD UNIVERSITY   (United States)

^d CARNEGIE MELLON UNIVERSITY   (United States)

^e IBM   (United States)

Author keywords

Defect classification; Excursion detection; Killer defect

Indexed keywords

DEFECTS; INSPECTION; MONITORING; PROCESS ENGINEERING; QUALITY ASSURANCE; SPURIOUS SIGNAL NOISE;

DEFECT CLASSIFICATIONS; EXCURSION DETECTIONS; KILLER DEFECTS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0033078399     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.744513     Document Type: Article

References (11)

1. R. K. Nurani, R. Akella, and A. J. Strojwas, "In-line defect sampling methodology in yield management: An integrated framework," IEEE Trans. Semiconduct. Manufact., vol. 9, pp. 506-517, Nov. 1996.
2. M. McIntyre, "Determining yield loss using in-line defect inspection results," in Proc. KLA Yield Management Seminar, 1994, available on request from KLA-Tencor Corporation, San Jose, CA 95161.
3. R. K. Nurani, R. Akella, A. J. Strojwas, R. Wallace, M. McIntyre, J. Shields, and I. Emami, "Development of an optical sampling strategy for wafer inspection," in Proc. Int. Symp. Semiconductor Manufacturing (ISSM'94), pp. 143-146.
4. L. Breaux and D. Kolar, "Automatic defect classification for effective yield management," Solid State Technol., pp. 89-96, Dec. 1996.
5. D. Coldren, "Practical considerations for integrating automatic defect classification (ADC) technology into mainstream production," in Proc. KLA Yield Management Seminar, 1997, available on request from KLA-Tencor Corporation, San Jose, CA 95161.
6. S. Ross, Introduction to Probability and Statistics for Engineers and Scientists. New York: Wiley, 1987.
7. W. Maly and J. Deszczka, "Yield estimation model for VLSI artwork evaluation," Electron. Lett., vol. 19, pp. 226-227, Mar. 1983.
8. R. K. Nurani, A. J. Strojwas, W. P. Maly, C. Ouyang, W. Shindo, R. Akella, M. G. McIntyre, and J. Derrett, "In-line yield prediction methodologies using patterned wafer inspection information," IEEE Trans. Semiconduct. Manufact., vol. 11, pp. 40-47, Feb. 1998.
9. T. J. Lorenzen and L. C. Vance, "The economic design of control charts: A unified approach," Technometrics, vol. 28, pp. 3-10, 1986.
10. K. Chen, R. Akella, I. Emami, and M. McIntyre, "Effective multistage test equipment capacity allocation for semiconductor fabrication yield enhancement," in Proc. Int. Symp. Semiconductor Manufacturing (ISSM'97), pp. P73-P75.
11. W. Shindo, E. H. Wang, R. Akella, and A. J. Strojwas, "Effective excursion detection and source isolation with defect inspection and classification," in Proc. Advanced Semiconductor Manufacturing Conf., 1997, pp. 146-149.