Increasing the instruction fetch rate via block-structured instruction set architectures

Proceedings of the Annual International Symposium on Microarchitecture

Volumn , Issue , 1996, Pages 191-200

  Hao, Eric ^a   Chang, Po Yung ^a   Evers, Marius ^a   Patt, Yale N ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; OPTIMIZATION; PROGRAM COMPILERS;

BLOCK ENLARGEMENT; INSTRUCTION FETCH RATE; INSTRUCTION SET ARCHITECTURES (ISA);

MICROCOMPUTERS;

EID: 0030379515     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)