A 1.3-ns 32-word × 32-bit three-port BiCMOS register file

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 6, 1996, Pages 758-765

  Chao, Chin Chieh ^a,b,c,d,e   Wooley, Bruce A ^a,b,e,f,g  

^a IEEE

^b Stanford University   (United States)

^c SUN MICROSYSTEMS   (United States)

^d NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^e STANFORD UNIVERSITY   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

^g LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR SEMICONDUCTOR DEVICES; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DESIGN; SCHEMATIC DIAGRAMS;

BIPOLAR MEMORY; CMOS MULTIPORT STATIC MEMORY CELL; READ ACCESS PATH;

SEMICONDUCTOR STORAGE;

EID: 0030166495     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.511018     Document Type: Article

References (11)

1. H. Shinohara, N. Matsumoto, K. Fujimori, Y. Tsujihashi, H. Nakao, S. Kato, Y. Horiba, and A. Tada, "A flexible multiport RAM compiler for data path," IEEE J. Solid-Slate Circuits, vol. 26, pp. 343-349, Mar. 1991.
2. H. Hara et al., "0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file," IEEE J. Solid-State Circuits, vol. 27, pp. 1579-1584. Nov. 1992.
3. A. L. Silburt, R. S. Phillips, G. F. R. Gibson, S. W. Wood, A. G. Bluschke, J. S. Fujimoto, S. P. Kornachuk, B. Nadeau-Dostie, R. K. Verma, and P. M. J. Diedrich, "A 180-MHz 0.8-μm BiCMOS modular memory family of DRAM and multiport SRAM," IEEE J. Solid-State Circuits, vol. 28, pp. 222-232, Mar. 1993.
4. N. Ide, H. Fukuhisa, Y. Kondo, T. Yoshida, M. Nagamatsu, J. Mori, I. Yamazaki, and K. Ueno, "A 320-MFLOPS CMOS floating-point processing unit for superscalar processors," IEEE J. Solid-State Circuits, vol. 28, pp. 352-361, Mar. 1993.
5. A. R. Alverez, Ed., BiCMOS Technology and Applications. Norwell, MA: Kluwer, 1989.
6. T. Takayanagi, K. Sawada, M. Takahashi, Y. Ito, M. Uchida, Y. Toyoshima, H. Hayashida, and M. Norishima, "2.6 Gbyte/sec bandwidth cache/TLB macro for high-performance RISC processor," in Proc. IEEE 1991 Custom Integrated Circuits Conf., May 1991, pp. 10.2.1-10.2.4.
7. M. J. Flynn, G. De Micheli, R. W. Dutton, B. A. Wooley, and F. Pease, "Stanford nanosecond arithmetic processor," Stanford University, CA, Status Report on two CIS seed research projects, Sept. 1991.
8. M. Horowitz, M. Slamowitz, B. Rose, and M. Johnson, "A 3.5 ns, 1 watt, ECL register file," ISSCC Dig. Tech. Papers, pp. 68-69, Feb. 1990.
9. D. E. Wingard, D. C. Stark, and M. A. Horowitz, "Circuit techniques for large CSEA SRAM's," IEEE J. Solid-State Circuits, vol. 27, pp. 908-919, June 1992.
10. T. C. Banwell, "Performance limitations of low-voltage regulators using only n-p-n transistors," IEEE J. Solid-State Circuits, vol. 26, pp. 77-80, Jan. 1991.
11. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed. New York: Wiley, 1993.