Effects of Erase Source Bias on Flash EPROM Device Reliability

IEEE Transactions on Electron Devices

Volumn 42, Issue 1, 1995, Pages 150-159

  San, K Tamer ^a   Kaya, C ^b   Ma, T P ^a  

^a YALE UNIVERSITY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); DATA STORAGE EQUIPMENT; ELECTRIC CURRENTS; ELECTRODES; ELECTRON TUNNELING; ELECTRONS; GATES (TRANSISTOR); PROM; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS;

DATA LOSS; DRAIN JUNCTION; ERASE SOURCE BIAS; FLASH ERASABLE PROM; GATE CURRENT; HOT ELECTRON INJECTION; LEAST POSITIVE OXIDE CHARGE; MEMORY CELL; POLYSILICON FLOATING GATE GENERATION; TUNNELING INDUCED HOLE GENERATION;

MOSFET DEVICES;

EID: 0029197224     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.370023     Document Type: Article

References (9)

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8. K. T. San and T. P. Ma, “Hole trapping characteristics in flash EPROMs and related reliability issues,” presented at IEEE Nonvolitile Semiconductor Memory Workshop, 1994.
9. A. Brand, K. Wu, S. Pan, and D. Chin, “Novel read disturb failure mechanism induced by flash cycling,” IEEE-IRPS, p. 127, 1993.