A novel cell structure suitable for a 3 volt operation, sector erase flash memory

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 599-602

  Onoda, H ^a   Kunori, Y ^a   Kobayashi, S ^a   Ohi, M ^a   Fukumoto, A ^a   Ajika, N ^a   Miyoshi, H ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CYTOLOGY; DATA TRANSFER; DATA TRANSFER RATES; ELECTRON DEVICES; FLASH MEMORY;

AREA REDUCTION; CELL STRUCTURE; DIVIDED BIT LINE; DRAIN DISTURB; HIGH DATA TRANSFER RATES; LOW-POWER DISSIPATION; SELECT TRANSISTOR; STACKED-GATE CELL;

CELLS;

EID: 85036499958     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307432     Document Type: Conference Paper

References (5)

1. N. Ajika et al, "A 5V Only 16M Bit Flash EEPROM Cell with a Simple Sucked Gate Structure, " EDM Tech. Digest, 1990, p. 115.
2. N. Kodama et al, "A SV Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies, " Sympo. on VLSI lech. Digest, 1991, p. 75.
3. H. Kume et al, "A 3. 42mm2 Flash Memory Cell Technology Comfortable to a Sector Erase, " Sympo. on VLSI Tech. Digest, 1991, p. 77.
4. T. Jinbo et al. 'A 5V-Only 16Mb Flash Memory with Sector-Erase Mode, " ISSCC Dig. Tech. Papers. 1992, p. 154.
5. M. Momodomi et al, "A 4-Mb NAND EEPROM with Tight Programmed Vt Distribution, " IEEE Solid State Circuits, vol. 26, 1991, p. 492.