Analysis of thin gate oxide degradation during fabrication of advanced CMOS ULSI circuits

IEEE Transactions on Electron Devices

Volumn 45, Issue 3, 1998, Pages 731-736

  Kim, Sang U ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS;

PLASMA CHARGING;

ULSI CIRCUITS;

EID: 0032028281     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.661235     Document Type: Article

References (6)

1. S. U. Kim, "A test structure for plasma charging monitor in advanced CMOS technologies," in Proc. 1996 Int. Integrated Reliability Workshop, pp. 57-61.
2. W. Abadeer, G. Hueckel, A. Acovic, and A. Ray, "Mechanism of stressinduced leakage due to plasma charging and effect of oxide thickness," in 1996 1st Int. Plasma Process-Induced Damage Conf., pp. 145-148.
3. M. Alavi, S. Jacobd, S. Ahmed, C. H. Chern, and P. Mcgregor, "Effect of MOS device scaling on process-induced gate charging," in 1997 2nd Int. Plasma Process-Induced Damage Conf., pp. 7-10.
4. S. Ma, C. Chi, A. Bayoumi, B. Langley, M. Cao, P. Marcoux, W. Greene, and G. Ray, "Plasma-induced charging damage on 30 A gate oxide antenna MOS capacitor structure during polysilicon gate etch," in 1997 2nd Int. Plasma Process-Induced Damage Conf., pp. 25-28.
5. C. Subramanian, J. Hayden, W. Taylor, M. Orlowski, and T. Mcnelly, "Reverse short-channel effect and channel length dependence of boron penetration in PMOSFET's," in IEDM Tech. Dig., 1995, pp. 423-426.
6. E. Hasegawa, M. Kawata, K. Ando, M. Makabe, M. Kitakata, A. Ishitani, L. Manchanda, M. L. Green, K. S. Krisch, and L. C. Feldman, "The impact of nitrogen profile engineering on ultra-thin nitrided oxide films for dual-gate CMOS ULSI," in IEDM Tech. Dig., 1995, pp. 327-330.