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Volumn , Issue , 1996, Pages 57-61
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Test structure for plasma process charging monitor in advanced CMOS technologies
a
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Author keywords
[No Author keywords available]
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Indexed keywords
ELECTRIC CURRENT MEASUREMENT;
GATES (TRANSISTOR);
INTEGRATED CIRCUIT LAYOUT;
INTEGRATED CIRCUIT TESTING;
LEAKAGE CURRENTS;
PLASMA APPLICATIONS;
RADIATION DAMAGE;
ULSI CIRCUITS;
PLASMA CHARGING;
PLASMA DAMAGE;
CMOS INTEGRATED CIRCUITS;
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EID: 0030360888
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (4)
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References (2)
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