Combining functional and structural approaches in test generation for digital systems

Microelectronics Reliability

Volumn 38, Issue 3, 1998, Pages 317-329

  Ubar, Raimund ^a  

^a TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DECISION THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; FUNCTIONS; MATHEMATICAL MODELS;

DECISION DIAGRAMS; TEST PATTERN RECOGNITION;

DIGITAL CIRCUITS;

EID: 0032021270     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(97)00192-3     Document Type: Article

References (33)

1. Robach, C. and Saucier, G., Microprocessor functional testing. Digest of Papers, IEEE 1980 Int. Test Conf., pp. 433-443.
2. Thatte, S. M. and Abraham, I. A., Test generation for microprocessors. IEEE Trans, Computers, 1980, 29, 429-441.
3. Gupta, A. G. and Armstrong, J. R., Functional fault modeling and simulation for VLSI devices. ACM/ IEEE 22nd Design Automation Conf., 1985, pp. 720-726.
4. Lin, T. and Su, S. Y. H., VLSI functional test pattern generation - a design and implementation. IEEE 1985 Int. Test Conf., pp. 922-929.
5. Geiselhardt, W., Mohrs, W. and Moeller, U., FLINTEST - Functional test generation for VLSI-circuits and systems. Microelectron. Reliab., 1989, 29(3), 357-364.
6. Giambiasi, N., Santucci, J. F., Courbis, A. L. and Pla, V., Test pattern generation for behavioral descriptions in VHDL. In Proc. VHDL Conf., Stockholm, 1991, pp. 228-234.
7. Santucci, J. F., Courbis, A.-L. and Giambiasi, N., Speed up of behavioral ATPG using a heuristic criterion. 30th ACM/IEEE Design Automation Conf., 1993, pp. 92-96.
8. Murray, B. T. and Hayes, J. P., Hierarchical test generation using precomputed tests for modules. IEEE 1988 Int. Test Conf., pp. 221-229.
9. Anirudhan, P. N. and Menon, P. R., Symbolic test generation for hierarchically modeled digital systems. IEEE 1989 Int. Test Conf., pp. 461-469.
10. Calhoun, J. D. and Brglez, F., A framework and method for hierarchical test generation. IEEE 1989 Int. Test Conf., pp. 480-490.
11. Sarfert, T. M., Markgraf, R., Trischler, E;. and Schulz. M. H., Hierarchical test pattern generation based on high-level primitives. IEEE 1989 Int. Test Conf., September 1989, pp. 470-479.
12. Bhattacharya, D. and Hayes, J. P., A hierarchical test generation methodology for digital circuits. JETTA: Theory and Application, 1990, 1, 103-123.
13. Roy, K. and Abraham, J. A., High-level test generation using data flow descriptions. In Proc. European Design Conf., March 1990, pp. 480-484.
14. Leenstra. J. and Spaanenburg, L., Hierarchical test assembly for macro based VLSI design. IEEE 1990 Int. Test Conf., pp. 520-529.
15. Kunda, R. P., Abraham, J. A. and Rathi, B. D., Speedup of test generation using high-level primitive. ACM/IEEE 27th Design Automation Conf., June 1990, pp. 580-586.
16. Karam, M., Leveugle, R. and Saucier, G., Hierarchical test generation based on delayed propagation. IEEE 1991 Int. Test Conf., pp. 739-747.
17. Rao, S. R., Pan, B. Y. and Armstrong, J. R., Hierarchical test generation for VHDL behavioral models. In Proc. EDAC, February 1993, pp. 175-183.
18. Lee, J. and Patel, J. H., Hierarchical test generation under intensive global functional constraints. In Proc. 29th ACM/IEEE Design Automation Conf., June 1992, pp. 261-266.
19. Min. H. B., Luh, H. A. and Rogers, W. A., Hierarchical test pattern generation: a cost model and implementation. IEEE Trans. CAD of Integrated Circuits and Systems, 1993, 12(7).
20. Steensma, W., Geurts, F., Catthoor, H. and De Man, Testability analysis in high level data path synthesis. J. Electron. Test.: Theory and Applications, 1993, 4, 43-56.
21. Yadavalli, S., Pomeranz, I. and Reddy, S. M., MUSTC-testing: multi-stage combinational test scheduling at the register-transfer level. In Proc. 8th Int. Conf. on VLSI Design, January 1995, pp. 110-115.
22. Abadir, M. S. and Breuer, M. A., A knowledge-based system for designing testable VLSI chips. IEEE Design and Test, 1985, pp. 56-68.
23. Freeman, S., Test generation for data path logic: The F-path method. IEEE J. Solid-State Circuits, 1988, 23, 421-427.
24. Akers, S. B., Binary decision diagrams. IEEE Trans. Computers, 1978, 27, 509-516.
25. Briant, R. E., Graph-based algorithms for Boolean function manipulation. IEEE Trans. Computers, 1986. C-35(8), 667-690.
26. Becker, B. and Drechsler, R., How many decomposition types do we need? European Design and Test Conf., Paris, 1995, pp. 438-443.
27. Corno, F., Gläser, U., Prinetto, P., Sonza Reorda, M. and Vierhaus, H. T., Improving topological ATPG with symbolic techniques. IEEE VLSI Test Symp., Princeton, NJ, April 1995, pp. 338-343.
28. Ubar, R., Beschreibung digitaler Einrichtungen mit AG für die Fehlerdiagnose. Nachrichtentechnik/Elektronik, 1980, 30(3), 96-102.
29. Ubar, R., Test synthesis with alternative graphs. IEEE Design and Test of Computers, Spring 1996, pp. 48-57.
30. Ubar, R., Test pattern generation for digital systems on the vector AG-model. 13th Int. Symp. on Fault Tolerant Computing, Milan, Italy, 1983, pp. 347-351.
31. Ubar, R. and Brik. M., Multi-level test generation and fault diagnosis for finite state machines. Lecture Notes in Computer Science 1150, Dependable Computing - EDCC-2. Springer-Verlag, Berlin, 1996, pp. 264-281.
32. Abraham, J. A., Fault modeling in VLSI. In VLSI Testing. North-Holland, Amsterdam, 1986, pp. 1-27.
33. Bochmann, D. and Ubar, R. (eds), Fehler in Automaten. VEB Verlag Technik, Berlin, 1989, p. 216.