-
5
-
-
0022291568
-
The design and construction of a rule base and an inference engine for test system diagnosis
-
Grillmeyer O., Wilkinson A.J. The design and construction of a rule base and an inference engine for test system diagnosis. IEEE Int. Test Conf., 1985, pp.857-867.
-
(1985)
IEEE Int. Test Conf.
, pp. 857-867
-
-
Grillmeyer, O.1
Wilkinson, A.J.2
-
6
-
-
0021593920
-
Diagnostic reasoning based on structure and behavior
-
Davis R. Diagnostic reasoning based on structure and behavior. Artificial Intelli-gence 24 (1984) 347-410.
-
(1984)
Artificial Intelli-Gence
, vol.24
, pp. 347-410
-
-
Davis, R.1
-
7
-
-
0026723173
-
Fault diagnosis using functional fault model for VHDL descriptions
-
Oct
-
Pitchumani V., Mayor P., Radia N. Fault diagnosis using functional fault model for VHDL descriptions. IEEE Int. Test Conf. Nashville, Oct., 1991., pp.327-337
-
(1991)
IEEE Int. Test Conf. Nashville
, pp. 327-337
-
-
Pitchumani, V.1
Mayor, P.2
Radia, N.3
-
10
-
-
0023564770
-
Diagnosis of BIST failures by PPSFP simulation
-
Washington, Sep
-
Waicukauski J.A., Gupta V.P., Patel S.T. Diagnosis of BIST failures by PPSFP simulation. 18th IEEE International Test Conference, Washington, Sep.l987,pp.480-484.
-
(1987)
18Th IEEE International Test Conference
, pp. 480-484
-
-
Waicukauski, J.A.1
Gupta, V.P.2
Patel, S.T.3
-
11
-
-
0024138096
-
GEMINI - A logic system for fault diagnosis based on set functions
-
Tokyo, June
-
Rajski J. GEMINI - a logic system for fault diagnosis based on set functions. 18th Int.Symposium on Fault Tolerant Computing, Tokyo, 1988, June,pp.292-297.
-
(1988)
18Th Int.Symposium on Fault Tolerant Computing
, pp. 292-297
-
-
Rajski, J.1
-
13
-
-
0022769976
-
Graph-based Algorithms for Boolean Function Manipulation
-
Aug
-
Bryant R.E. Graph-based Algorithms for Boolean Function Manipulation. IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp.667-690.
-
(1986)
IEEE Trans. Computers
, vol.C-35
, Issue.8
, pp. 667-690
-
-
Bryant, R.E.1
-
14
-
-
84959030384
-
Optimization of fault localization procedures in computer hardware
-
Vilnius,Lithuania, (in Russian)
-
Ubar R., Evartson T. Optimization of fault localization procedures in computer hardware. In "CAD in electronical and computer engineering ", Part I., Vilnius,Lithuania, 1981, pp.175-184 (in Russian).
-
(1981)
CAD in Electronical and Computer Engineering
, pp. 175-184
-
-
Ubar, R.1
Evartson, T.2
-
15
-
-
84959030385
-
Hierarchical test generation for finite state machines
-
Tallinn, October
-
Brik M., Ubar R. Hierarchical test generation for finite state machines. Proc. of the 4th Baltic Electronics Conference. Tallinn, October 1994, pp.319-324.
-
(1994)
Proc. Of the 4Th Baltic Electronics Conference
, pp. 319-324
-
-
Brik, M.1
Ubar, R.2
-
16
-
-
46449113761
-
High Level Test Pattern Generation for VHDL Circuits
-
Montpellier, France, June 12-14
-
Sallay B, Petri A., Tilly K., Pataricza A. High Level Test Pattern Generation for VHDL Circuits. IEEE European Test Workshop, Montpellier, France, June 12-14,1996, pp. 201-205.
-
(1996)
IEEE European Test Workshop
, pp. 201-205
-
-
Sallay, B.1
Petri, A.2
Tilly, K.3
Pataricza, A.4
-
18
-
-
0029778025
-
-
The European Design & Test Conference, Paris, March 11-14
-
Gulbins M., Straube B. Applying Behavioral Level Test Generation to High-Level Design Validation. The European Design & Test Conference, Paris, March 11-14,1996, p. 613.
-
(1996)
Applying Behavioral Level Test Generation to High-Level Design Validation
, pp. 613
-
-
Gulbins, M.1
Straube, B.2
-
20
-
-
0026153304
-
And verification for highly sequential circuits
-
May
-
Ghosh A., Devadas S., Newton A.R. Test generation and verification for highly sequential circuits. IEEE Trans, on CAD, Vol.10, No.S, May 1991.
-
(1991)
IEEE Trans, on CAD
, vol.10
, Issue.S
-
-
Ghosh, A.1
Devadas, S.2
Newton, A.R.3
Generation, T.4
-
21
-
-
0019030438
-
Test Generation for Microprocessors
-
Thatte S.M., Abraham J.A. Test Generation for Microprocessors, IEEE Trans.Computers, Vol.29, 1980, pp.429-441.
-
(1980)
IEEE Trans.Computers
, vol.29
, pp. 429-441
-
-
Thatte, S.M.1
Abraham, J.A.2
-
22
-
-
10444272628
-
Binary Decision Diagrams and Applications for VLSI CAD
-
Minato S. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publish., 1996, 141 p.
-
(1996)
Kluwer Academic Publish.
, pp. 141
-
-
Minato, S.1
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