Analytical delay model for RLC interconnects

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 237-240

  Kahng, Andrew B ^a   Muddu, Sudhakar ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; ELECTRIC WIRING; ESTIMATION; MATHEMATICAL MODELS; POLES AND ZEROS; POLYNOMIALS; TOPOLOGY; TRANSFER FUNCTIONS; TREES (MATHEMATICS); VLSI CIRCUITS;

ANALYTICAL DELAY MODEL; DELAY ESTIMATE; IMPULSE RESPONSE; INDUCTANCE; INDUCTANCE EFFECTS; INTERCONNECTION LINES; RLC INTERCONNECTS;

ELECTRIC DELAY LINES;

EID: 0029696654     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)