SCOPUS 정보 검색 플랫폼

Analog Integrated Circuits and Signal Processing

Volumn 5, Issue 1, 1994, Pages 19-30

A simplified synthesis of transmission lines with a tree structure

(5) Zhou, D a Su, S a Tsui, F a Gao, D S b Cong, J S c

a UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE (United States)

b SUN MICROSYSTEMS (United States)

c UNIVERSITY OF CALIFORNIA (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WAVEFORMS; INTEGRATED CIRCUIT LAYOUT; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; PERFORMANCE; POLES AND ZEROS; TREES (MATHEMATICS);

CHIP TO CHIP INTERCONNECTION; CIRCUIT PROPERTY; DESIGN PARAMETER; INTERCONNECTION DELAY; LIMITING FACTOR; MATHEMATICAL METHODS; TRANSISTOR SWITCHING SPEED;

INTEGRATED CIRCUITS;

EID: 0028317790 PISSN: 09251030 EISSN: 15731979 Source Type: Journal
DOI: 10.1007/BF01673903 Document Type: Article

Times cited : (22)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.