Low power neuron-MOS technology for high-functionality logic gate synthesis

IEICE Transactions on Electronics

Volumn E80-C, Issue 7, 1997, Pages 924-929

  Kwon, Ho Yup ^a   Kotani, Koji ^a   Shibata, Tadashi ^a   Ohmi, Tadahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

Deep threshold; Full adder; Low power; Neuron MOS; Number detector

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MOS DEVICES; OPTIMIZATION;

NEURON METAL OXIDE SEMICONDUCTOR TECHNOLOGY;

LOGIC GATES;

EID: 0031190331     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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