Comparison of parallel multipliers with neuron MOS and CMOS technologies

IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Volumn , Issue , 1996, Pages 488-491

  Hirose, Kei ^a   Yasuura, Hiroto ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; ERRORS; GATES (TRANSISTOR); LOGIC DESIGN; MOSFET DEVICES; MULTIPLYING CIRCUITS; VLSI CIRCUITS;

BINARY LOGIC CIRCUIT; FLOATING GATE POTENTIAL; NEURON MOS TRANSISTORS; PARALLEL MULTIPLIERS;

LOGIC CIRCUITS;

EID: 0030396433     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)