Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages

  Kotani, Koji ^a   Shibata, Tadashi ^a   Imai, Makoto ^a   Ohmi, Tadahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MOS DEVICES; THRESHOLD ELEMENTS;

AUTO THRESHOLD ADJUSTMENT; CLOCK DRIVEN SWITCHING TRANSISTOR; FLOATING GATE CHARGE;

LOGIC CIRCUITS;

EID: 0029253825     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)