Symbolic two-level minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 7, 1997, Pages 692-708

  Villa, Tiziano ^a,b,c   Saldanha, Alex ^a,b,c   Brayton, Robert K ^a,b,c   Sangiovanni Vincentelli, Alberto L ^a,b,c  

^a PARADES   (Italy)

^b CADENCE DESIGN SYSTEMS   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY CODES; ENCODING (SYMBOLS); FINITE AUTOMATA; MINIMIZATION OF SWITCHING NETS; SEQUENTIAL MACHINES;

SYMBOLIC MINIMIZATION; TWO LEVEL SEQUENTIAL MACHINES;

COMPUTER AIDED LOGIC DESIGN;

EID: 0031175765     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.644031     Document Type: Article

References (16)

1. R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Boston, MA: Kluwer, 1984.
2. M. Ciesielski, J.-J. Shen, and M. Davio, "A unified approach to input-output encoding for FSM state assignment," Proc. Design Automation Conf., June 1991, pp. 176-181.
3. S. Devadas and R. Newton, "Exact algorithms for output encoding, state assignment and four-level Boolean minimization," IEEE Trans. Computer-Aided Design, vol. 10, pp. 13-27, Jan. 1991.
4. E. I. Goldberg, "Matrix formulation of constrained encoding problems in optimal PLA synthesis," Preprint 19, Inst. Eng. Cybern., Acad. Sci. Belarus, 1993.
5. _, "Face embedding by componentwise construction of intersecting cubes," Preprint l, Inst. Eng. Cybern., Acad. Sci. Belarus, 1995.
6. G. De Micheli, "Symbolic design of combinational and sequential logic circuits implemented by two-level logic macros," IEEE Trans. Computer-Aided Design, pp. 597-616, Oct. 1986.
7. G. De Micheli, R. Brayton, and A. Sangiovanni-Vincentelli, "Optimal state assignment for finite state machines," IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 269-285, July 1985
8. G. De Micheli, T. Villa, and A. Sangiovanni-Vincentelli, "Computer-aided synthesis of PLA-based finite state machines," Proc. Int. Conf. Computer-Aided Design, Sept. 1983, pp. 154-157
9. R. Rudell and A. Sangiovanni-Vincentelli, "Multiple-valued minimiza-tion for PLA optimization," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 727-750, Sept. 1987.
10. A. Saldanha and R. Katz, "PLA optimization using output encoding," Proc. Int. Conf. Computer-Aided Design, Nov. 1988, pp. 478181.
11. A. Saldanha, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli, "Satisfaction of input and output encoding constraints," IEEE Trans. Computer-Aided Design, vol. 13, pp. 589-602, May 1994.
12. G. Saucier, C. Duff, and F. Poirot, "State assignment using a new embedding method based on an intersecting cube theory," Proc. Design Automation Conf., June 1989, pp. 321-326
13. Y. Su and P. Cheung, "Computer minimization of multi-valued switch-ing functions," IEEE Trans. Comput., vol. C-21, pp. 995-1003, Sept. 1972
14. J. Tracey, "Internal state assignment for asynchronous sequential ma-chines," IRE Trans. Electron. Comput., pp. 551-560, Aug. 1966.
15. T. Villa and A. Sangiovanni-Vincentelli, "NOVA: State assignment for optimal two-level logic implementations," IEEE Trans. Computer-Aided Design, vol. 9, pp. 905-924, Sept. 1990.
16. S. Yang and M. Ciesielski, "Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization," IEEE Trans. Computer-Aided Design, vol. 10, pp. 4-12, Jan. 1991.