-
1
-
-
0011808050
-
A programmed algorithm for assigning internal codes to sequential machines
-
Aug.
-
D. B. Armstrong, “A programmed algorithm for assigning internal codes to sequential machines,” IRE Trans. Electron. Comput., vol. EC-11, pp. 466-472, Aug. 1962.
-
(1962)
IRE Trans. Electron. Comput.
, vol.EC-11
, pp. 466-472
-
-
Armstrong, D.B.1
-
2
-
-
0003567872
-
-
Hingham, MA: Kluwer Academic
-
R. K. Brayton, G. D. Hatchel. C. T. McMullen, A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Hingham, MA: Kluwer Academic, 1984.
-
(1984)
Logic Minimization Algorithms for VLSI Synthesis
-
-
Brayton, R.K.1
Hatchel, G.D.2
McMullen, C.T.3
Sangiovanni-Vincentelli, A.L.4
-
3
-
-
0024923638
-
Multiple-val-ued minimization based on graph coloring
-
also, in Tech. Rep., TR-89-CSE-4. Dept, of Electrical and Computer Engineering, Univ. of Massachusetts, Amherst.
-
M. J. Ciesielski, S. Yang, and M. A. Perkowski, “Multiple-val-ued minimization based on graph coloring,” in Proc. 1989 IEEE Int. Conf. on Computer Design. Oct. 1989; also, in Tech. Rep., TR-89-CSE-4. Dept, of Electrical and Computer Engineering, Univ. of Massachusetts, Amherst. 1989.
-
(1989)
Proc. 1989 IEEE Int. Conf. on Computer Design. Oct. 1989
-
-
Ciesielski, M.J.1
Yang, S.2
Perkowski, M.A.3
-
4
-
-
84893561614
-
Optimal state assignment for finite state machines
-
July
-
G. DeMicheli, R. K. Brayton, and A. Sangiovanni-Vincentelli, “Optimal state assignment for finite state machines,” IEEE Trans. Computer-Aided Design. vol. CAD-4, pp. 269–284, July 1985.
-
(1985)
IEEE Trans. Computer-Aided Design
, vol.CAD-4
, pp. 269-284
-
-
DeMicheli, G.1
Brayton, R.K.2
Sangiovanni-Vincentelli, A.3
-
5
-
-
0022791754
-
Symbolic design of combinational and sequential logic circuits implemented by two-level logic macros
-
Oct.
-
G. DeMicheli, “Symbolic design of combinational and sequential logic circuits implemented by two-level logic macros,” IEEE Trans. Computer-Aided Design. vol. CAD-5, pp. 597–616, Oct. 1986.
-
(1986)
IEEE Trans. Computer-Aided Design
, vol.CAD-5
, pp. 597-616
-
-
DeMicheli, G.1
-
6
-
-
0024168944
-
Boolean decomposition in multi-level logic optimization
-
S. Devadas, A. R. Wang, A. R. Newton, and A. Sangiovanni-Vincentelli, “Boolean decomposition in multi-level logic optimization.” in IEEE Int. Conf. on Computer-Aided Design, Dig. Tech. Papers, 1988. pp. 290–293.
-
(1988)
IEEE Int. Conf. on Computer-Aided Design, Dig. Tech. Papers
, pp. 290-293
-
-
Devadas, S.1
Wang, A.R.2
Newton, A.R.3
Sangiovanni-Vincentelli, A.4
-
7
-
-
84938021013
-
The coding of internal states of sequential circuits
-
Oct.
-
T. A. Dolotta and E. J. McCluskey, “The coding of internal states of sequential circuits,” IRE Trans. Electron. Comput., vol. EC-13, 549–562, Oct. 1964.
-
(1964)
IRE Trans. Electron. Comput.
, vol.EC-13
, pp. 549-562
-
-
Dolotta, T.A.1
McCluskey, E.J.2
-
8
-
-
0004127488
-
Computer and Intractability
-
San Francisco, CA: Freeman
-
M. R. Garey and D. S. Johnson. Computer and Intractability, San Francisco, CA: Freeman. 1979.
-
-
-
Garey, M.R.1
Johnson, D.S.2
-
9
-
-
0004292536
-
Introduction to Switching Theory and Logical Design
-
New York: Wiley
-
F. J. Hill and G. R. Peterson, Introduction to Switching Theory and Logical Design. New York: Wiley, 1974.
-
-
-
Hill, F.J.1
Peterson, G.R.2
-
10
-
-
0016102508
-
MINI: A heuristic approach for logic minimization
-
Sept.
-
S. J. Hong, R. G. Cain and D. L. Ostapko, “MINI: A heuristic approach for logic minimization,” IBM J. Res. Develop., pp. 443–458, Sept. 1974.
-
(1974)
IBM J. Res. Develop.
, pp. 443-458
-
-
Hong, S.J.1
Cain, R.G.2
Ostapko, D.L.3
-
11
-
-
29544443406
-
Secondary state assignment for sequential machines
-
June
-
Z. Kohavi, “Secondary state assignment for sequential machines,” IEEE Trans. Electron. Comput., pp. 193–203, June 1964.
-
(1964)
IEEE Trans. Electron. Comput.
, pp. 193-203
-
-
Kohavi, Z.1
-
12
-
-
0023313534
-
Generating essential prime implicants for a Boolean function with multiple-valued inputs
-
Mar.
-
Y. S. Kuo, “Generating essential prime implicants for a Boolean function with multiple-valued inputs.” IEEE Trans. Comput., vol. 36, pp. 356–359. Mar. 1987.
-
(1987)
IEEE Trans. Comput.
, vol.36
, pp. 356-359
-
-
Kuo, Y.S.1
-
13
-
-
84912798220
-
Encoding symbolic inputs for multi-level logic implementations, in
-
May
-
S. Malik, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, “Encoding symbolic inputs for multi-level logic implementations, in Proc. Int. Workshop on Logic Synthesis, MCNC, May 1989.
-
(1989)
Proc. Int. Workshop on Logic Synthesis, MCNC
-
-
Malik, S.1
Brayton, R.K.2
Sangiovanni-Vincentelli, A.L.3
-
14
-
-
33845331515
-
Minimization of Boolean functions
-
Nov.
-
E. J. McCluskey, “Minimization of Boolean functions,” Bell Syst. Tech. J., vol. 35. pp. 1417–1445. Nov. 1956.
-
(1956)
Bell Syst. Tech. J
, vol.35
, pp. 1417-1445
-
-
McCluskey, E.J.1
-
15
-
-
84941496101
-
A new approach to exact minimization of Boolean functions with multiple-valued inputs
-
Portland State Univ.
-
M. A. Perkowski and P. Wu, “A new approach to exact minimization of Boolean functions with multiple-valued inputs,” Tech. Rep. 38/1988, DIADES Research Group, Dept, of Electrical Engineering, Portland State Univ., 1988.
-
(1988)
Tech. Rep. 38/1988, DIADES Research Group, Dept, of Electrical Engineering
-
-
Perkowski, M.A.1
Wu, P.2
-
18
-
-
0021510779
-
Input variable assignment and output phase optimization of PLA’s
-
Oct.
-
T. Sasao, “Input variable assignment and output phase optimization of PLA’s,” IEEE Trans. Comput., vol. C-33, pp. 879–894, Oct. 1984.
-
(1984)
IEEE Trans. Comput.
, vol.C-33
, pp. 879-894
-
-
Sasao, T.1
-
19
-
-
0015316210
-
State minimization of asynchronous sequential machines using graph techniques
-
Mar.
-
G. Saucier, “State minimization of asynchronous sequential machines using graph techniques,” IEEE Trans. Comput., vol. C-21, pp. 282–288, Mar. 1972.
-
(1972)
IEEE Trans. Comput.
, vol.C-21
, pp. 282-288
-
-
Saucier, G.1
-
20
-
-
1842763479
-
Internal state assignment for asynchronous sequential machines
-
Aug.
-
J. H. Tracey, “Internal state assignment for asynchronous sequential machines,” IEEE Trans. Electron. Comput., pp. 551-560, Aug. 1966.
-
(1966)
IEEE Trans. Electron. Comput.
, pp. 551-560
-
-
Tracey, J.H.1
-
21
-
-
84911259168
-
Algorithms for state assignments for finite state machines for optimal two-level logic implementations
-
May
-
T. Villa and A. L. Sangiovanni-Vincentelli, “Algorithms for state assignments for finite state machines for optimal two-level logic implementations,” in Proc. Int. Workshop on Logic Synthesis, MCNC, May 1989.
-
(1989)
Proc. Int. Workshop on Logic Synthesis, MCNC
-
-
Villa, T.1
Sangiovanni-Vincentelli, A.L.2
|