Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 5, Issue 4, 1986, Pages 597-616

  De Micheli, Giovanni ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84939697365     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1986.1270230     Document Type: Article

References (23)

1. A. V. Aho, J. E. Hopcroft, and J. D. Ullman, The Design and Analysis of Computer Algorithms. New York: Addison Wesley, 1974.
2. R. Brayton, G. D. Hachtel, C. McMullen, and A. L. Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
3. R. Brayton, N. Brenner, C. Chen, G. De Micheli, C. McMullen, and R. Otten “The Yorktown Silicon Compiler,” in Proc. Int. Symp. on Circuit and Systems (Kioto, Japan), June 1985, pp. 391–394.
4. G. De Micheli, R. Brayton, and A. L. Sangiovanni-Vincentelli, “KISS: A program for optimal state assignment of finite state machines,” in Proc. ICCAD (Santa Clara), Nov. 1984.
5. G. De Micheli, R. Brayton, and A. L. Sangiovanni-Vincentelli, “Optimal state assignment for finite state machines,” IEEE Trans. Computer-Aided Design, vol. CAD-4, no. 3, 269–284, July 1985.
6. G. De Micheli, “Symbolic minimization of logic functions,” in Int. Conf. on Comp. Aid. Des., (Santa Clara), Nov. 1985, pp. 293–295.
7. T. A. Dolotta and E. J. McCluskey, “The coding of internal states of sequential machines,” IEEE Trans. Electron Comput., vol. EC- 13, pp. 549–562, Oct. 1964.
8. M. R. Garey and D. S. Johnson, Computers and Intractability. San Francisco: W. H. Freeman, 1978.
9. J. Hartmanis and R. E. Stearns, Algebraic Structure Theory of Sequential Machines. Englewood Cliffs, NJ: Prentice Hall, 1966.
10. F. Hill and G. Peterson, Introduction to Swtiching Theory and Logical Design. New York: Wiley, 1981.
11. S. J. Hong, R. G. Cain and D. L. Ostapko, “MINI: A heuristic approach for logic minimization,” IBM J. Res. Develop., vol. 18, pp. 443–458, Sept. 1974.
12. S. K. Hurst, “Multiple-valued logic—Its status and its future,” IEEE Trans. Comput., vol. C-33, pp. 1160–1179, Dec. 1984.
13. A. Nichols and A. Bernstein, “State assignment in combinational networks,” IEEE Trans. Electron Comput., vol. EC-14, pp. 343–349, June 1965.
14. E. J. McCluskey, “Minimization of Boolean functions,” Bell. Lab. Tech. J., vol. 35, p. 1417–1444, Apr. 1956.
15. E. L. Post, “Introduction to a general theory of elementary propositions,” Amer. J. Math., vol. 43, pp. 163–185, 1921.
16. F. Preparata and R. Yeh, Introduction to Discrete Structures. Addison Weseley, 1973.
17. D. Rine, Computer Science and Multiple-Valued Logic. New York: North Holland, 1977.
18. R. Rudell and A. Sangiovanni-Vincentelli, “ESPRESSO-MV: Algorithms for Multivalued Logic Minimization,” in Proc. Custom Int. Circ. Conf, (Portland, OR), May 1985.
19. T. Sasao, “Input variable assignment and output phase assignment of PLA’s,” IBM Res. Rep., no. 1003, June 1983.
20. J. R. Story, H. J. Harrison, and E. A. Reinhard, “Optimum state assignment for synchronous sequential circuits,” IEEE Trans. Comput., vol. C-21, pp. 1365–1373, Dec. 1972.
21. S. Y. H. Su and P. T. Cheung, “Computer minimization of multivalued switching functions,” IEEE Trans. Comput., vol. C-21, pp. 995–1003, 1972.
22. H.C. Torng, “An algorithm for finding secondary assignments of synchronous sequential circuits,” IEEE Trans. Comput., vol. C-17, pp. 416–469, May 1968.
23. P. Weiner and E. J. Smith, “Optimization of reduced dependencies for synchronous sequential machines,” IEEE Trans. Electron Comput., vol. EC-16, pp. 835–847, Dec. 1967.